Datasheet

t
d13
RD1, RD2
‡
(read RBR)
RCLK
t
d14
t
d14
t
d12
Parity StopStart Data Bits 5- 8
Sample Clock
TL16C450 Mode:
Sample Clock
SIN
INTRPT
(data ready)
INTRPT
(RCV error)
RD1
, RD2
‡
(read LSR)
50%
50%
50%
Active
Active
50%
50%
50%
50%
8 CLKs
TL16C550D , , TL16C550DI
www.ti.com .................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008
PARAMETER MEASUREMENT INFORMATION (continued)
A. The RD2 signal is applicable only to the PT and PFB packages.
Figure 8. Receiver Timing Waveforms
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