Datasheet

SYSTEM TIMING REQUIREMENTS
TL16C550D , , TL16C550DI
SLLS597E – APRIL 2004 – REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com
over recommended ranges of supply voltage and operating free-air temperature
ALT. SYMBOL TEST CONDITIONS MIN MAX UNIT
t
cR
Cycle time, read (t
w7
+ t
d8
+ t
d9
) RC 87 ns
t
cW
Cycle time, write (t
w6
+ t
d5
+ t
d6
) WC 87 ns
f = 16 MHz Max, V
CC
= 2.5 V,
25
See Figure 5
f = 20 MHz Max, V
CC
= 3.3 V,
20
See Figure 5
t
w1
Pulse duration, clock high t
XH
ns
f = 24 MHz Max, V
CC
= 5 V,
18
See Figure 5
f = 48 MHz Max, V
CC
= 3.3 V,
See Figure 5 8
(ZQS package only)
f = 16 MHz Max, V
CC
= 2.5 V,
25
See Figure 5
f = 20 MHz Max, V
CC
= 3.3 V,
20
See Figure 5
t
w2
Pulse duration, clock low t
XL
ns
f = 24 MHz Max, V
CC
= 5 V,
18
See Figure 5
f = 48 MHz Max, V
CC
= 3.3 V,
See Figure 5 8
(ZQS package only)
t
w5
Pulse duration, ADS low tADS See Figure 6 and Figure 7 9 ns
t
w6
Pulse duration, WR t
WR
See Figure 6 40 ns
t
w7
Pulse duration, RD t
RD
See Figure 7 40 ns
t
w8
Pulse duration, MR t
MR
1 µ s
t
su1
Setup time, address valid before ADS↑ t
AS
See Figure 6 and Figure 7 8 ns
t
su2
Setup time, CS valid before ADS↑ t
CS
t
su3
Setup time, data valid before WR1↑ or WR2 ↓ tDS See Figure 6 15 ns
t
su4
Setup time, CTS↑ before midpoint of stop bit See Figure 17 10 ns
t
h1
Hold time, address low after ADS↑ t
AH
See Figure 6 and Figure 7 0 ns
t
h2
Hold time, CS valid after ADS↑ t
CH
t
h3
Hold time, CS valid after WR1 ↑ or WR2 ↓ t
WCS
See Figure 6 10 ns
t
h4
Hold time, address valid after WR1↑ or WR2 ↓ t
WA
t
h5
Hold time, data valid after WR1↑ or WR2 ↓ t
DH
See Figure 6 5 ns
t
h6
Hold time, CS valid after RD1↑ or RD2 ↓ t
RCS
See Figure 7 10 ns
t
h7
Hold time, address valid after RD1↑ or RD2 ↓ t
RA
See Figure 6 20 ns
t
d4
Delay time, CS valid before WR1↓ or WR2 ↑
(1)
t
CSW
See Figure 6 7 ns
t
d5
Delay time, address valid before WR1↓ or WR2 ↑
(1)
t
AW
t
d6
Delay time, write cycle, WR1↑ or WR2 ↓ to ADS↓ t
WC
See Figure 6 40 ns
t
d7
Delay time, CS valid to RD1↓ or RD2 ↑
(1)
 tCSR
See Figure 7 7 ns
t
d8
Delay time, address valid to RD1↓ or RD2 ↑
(1)
t
AR
t
d9
Delay time, read cycle, RD1↑ or RD2 ↓ to ADS↓ t
RC
See Figure 7 40 ns
t
d10
Delay time, RD1↓ or RD2 ↑ to data valid t
RVD
C
L
= 75 pF, Figure 7 45 ns
t
d11
Delay time, RD1↑ or RD2 ↓ to floating data t
HZ
C
L
= 75 pF, See Figure 7 20 ns
(1) Only applies when ADS is low.
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