Datasheet

 
  
  
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SLLS177H − MARCH 1994 − REVISED JANUARY 2006
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Receiver
Buffer
Register
Divisor
Latch (LS)
Divisor
Latch (MS)
Baud
Generator
Receiver
FIFO
Line
Status
Register
Transmitter
Holding
Register
Modem
Control
Register
Modem
Status
Register
Line
Control
Register
Transmitter
FIFO
Interrupt
Enable
Register
Interrupt
Identification
Register
FIFO
Control
Register
Select
and
Control
Logic
Interrupt
Control
Logic
S
e
l
e
c
t
Data
Bus
Buffer
BAUDOU
T
SIN
RCLK
SOUT
CTS
DTR
DSR
DCD
RI
OUT1
OUT2
INTRP
T
A0
D(7−0)
Internal
Data Bus
A1
A2
CS0
CS1
CS2
ADS
MR
RD1
RD2
WR1
WR2
DDIS
TXRDY
XIN
XOUT
R
XRDY
S
e
l
e
c
t
Receiver
Shift
Register
Receiver
Timing and
Control
Transmitter
Timing and
Control
Transmitter
Shift
Register
Modem
Control
Logic
8
V
CC
V
SS
Power
Supply
RTS
Autoflow
Control
(AFE)
8
8
8
8
8
8
8