Datasheet
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
programmable baud generator (continued)
Driver
Optional
Driver
External
Clock
Optional
Clock
Output
Oscillator Clock
to Baud Generator
Logic
XIN
XOUT
V
CC
Crystal
XIN
RX2
V
CC
XOUT
C1
R
P
C2
Oscillator Clock
to Baud Generator
Logic
TYPICAL CRYSTAL OSCILLATOR NETWORK
CRYSTAL
R
P
RX2 C1 C2
3.072 MHz 1 MΩ 1.5 kΩ 10−30 pF 40−60 pF
1.8432 MHz 1 MΩ 1.5 kΩ 10−30 pF 40−60 pF
Figure 23. Typical Clock Circuits
receiver buffer register (RBR)
The ACE receiver section consists of a receiver shift register (RSR) and a RBR. The RBR is actually a 16-byte
FIFO. Timing is supplied by the 16× receiver clock (RCLK). Receiver section control is a function of the ACE
line control register.
The ACE RSR receives serial data from SIN. The RSR then concatenates the data and moves it into the RBR
FIFO. In the TL16C450 mode, when a character is placed in the RBR and the received data available interrupt
is enabled (IER0 = 1), an interrupt is generated. This interrupt is cleared when the data is read out of the RBR.
In the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register.
scratch register
The scratch register is an 8-bit register that is intended for the programmer’s use as a scratchpad in the sense
that it temporarily holds the programmer’s data without affecting any other ACE operation.
transmitter holding register (THR)
The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a
16-byte FIFO. Timing is supplied by BAUDOUT
. Transmitter section control is a function of the ACE line control
register.
The ACE THR receives data off the internal data bus and when the shift register is idle, moves it into the TSR.
The TSR serializes the data and outputs it at SOUT. In the TL16C450 mode, if the THR is empty and the
transmitter holding register empty (THRE) interrupt is enabled (IER1 = 1), an interrupt is generated. This
interrupt is cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated
based on the control setup in the FIFO control register.