Datasheet
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
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PRINCIPLES OF OPERATION
interrupt enable register (IER)
The IER enables each of the five types of interrupts (refer to Table 5) and enables INTRPT in response to an
interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents
of this register are summarized in Table 3 and are described in the following bullets.
D Bit 0: When set, this bit enables the received data available interrupt.
D Bit 1: When set, this bit enables the THRE interrupt.
D Bit 2: When set, this bit enables the receiver line status interrupt.
D Bit 3: When set, this bit enables the modem status interrupt.
D Bits 4 through 7: These bits are not used (always cleared).
interrupt identification register (IIR)
The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with
most popular microprocessors.
The ACE provides four prioritized levels of interrupts:
D Priority 1 − Receiver line status (highest priority)
D Priority 2 − Receiver data ready or receiver character time-out
D Priority 3 − Transmitter holding register empty
D Priority 4 − Modem status (lowest priority)
When an interrupt is generated, the IIR indicates that an interrupt is pending and encodes the type of interrupt
in its three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3 and
described in Table 5. Detail on each bit is as follows:
D Bit 0: This bit is used either in a hardwire prioritized or polled interrupt system. When bit 0 is cleared, an
interrupt is pending If bit 0 is set, no interrupt is pending.
D Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 3
D Bit 3: This bit is always cleared in TL16C450 mode. In FIFO mode, bit 3 is set with bit 2 to indicate that a
time-out interrupt is pending.
D Bits 4 and 5: These two bits are not used (always cleared).
D Bits 6 and 7: These bits are always cleared in TL16C450 mode. They are set when bit 0 of the FIFO control
register is set.