Datasheet

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SLLS177H − MARCH 1994 − REVISED JANUARY 2006
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
t
d13
(see Note B)
t
d14
Stop
Sample Clock
SIN
(first byte)
Active
RD
(RD RBR)
RXRDY
See Note A
50%
50%
50%
NOTE A: This is the reading of the last byte in the FIFO.
Figure 11. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
t
d13
(see Note B)
t
d14
Sample Clock
SIN
(first byte that reaches
the trigger level)
Active
RD
(RD RBR)
RXRDY
See Note A
50%
50%50%
NOTES: A. This is the reading of the last byte in the FIFO.
B. For a time-out interrupt, t
d13
= 9 RCLKs.
Figure 12. Receiver Ready (RXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)