Datasheet

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SLLS177H − MARCH 1994 − REVISED JANUARY 2006
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
t
d13
(see Note A)
t
d14
Stop
Data Bits 5−8
Sample Clock
SIN
Trigger Level
INTRPT
(FCR6, 7 = 0, 0)
INTRPT
Line Status
Interrupt (LSI)
t
d14
RD1
(RD LSR)
RD1
(RD RBR)
Active
Active
(FIFO at or above
trigger level)
(FIFO below
trigger level)
50%50%
50%
50%
50%
50%
NOTE A: For a time-out interrupt, t
d13
= 9 RCLKs.
Figure 9. Receive FIFO First Byte (Sets DR Bit) Waveforms
t
d13
(see Note A)
t
d14
Stop
Top Byte of FIFO
Sample Clock
SIN
Time-Out or
Trigger Level
Interrupt
Line Status
Interrupt (LSI)
t
d13
(FIFO at or above
trigger level)
(FIFO below
trigger level)
RD1, RD2
(RD LSR)
RD1
, RD2
(RD RBR)
Active Active
t
d14
Previous Byte
Read From FIFO
50%
50%
50%50%
50%
50% 50%
NOTE A: For a time-out interrupt, t
d13
= 9 RCLKs.
Figure 10. Receive FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms