Datasheet

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SLLS177H − MARCH 1994 − REVISED JANUARY 2006
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
receiver switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 8)
PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT
t
d12
Delay time, RCLK to sample t
SCD
8 10 ns
t
d13
Delay time, stop to set INTRPT or read
RBR to LSI interrupt or stop to RXRDY
↓
t
SINT
8, 9, 10,
11, 12
1
RCLK
cycle
t
d14
Delay time, read RBR/LSR to reset INTRPT t
RINT
8, 9, 10,
11, 12
C
L
= 75 pF 70 ns
NOTE 8: In the FIFO mode, the read cycle (RC) = 425 ns (min) between reads of the receive FIFO and the status registers (interrupt identification
register or line status register).
transmitter switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT
t
d15
Delay time, initial write to transmit start t
IRS
13 8 24
baudout
cycles
t
d16
Delay time, start to INTRPT t
STI
13 8 10
baudout
cycles
t
d17
Delay time, WR (WR THR) to reset INTRPT t
HR
13 C
L
= 75 pF 50 ns
t
d18
Delay time, initial write to INTRPT (THRE
†
) t
SI
13 16 34
baudout
cycles
t
d19
Delay time, read IIR
†
to reset INTRPT
(THRE
†
)
t
IR
13 C
L
= 75 pF 35 ns
t
d20
Delay time, write to TXRDY inactive t
WXI
14,15 C
L
= 75 pF 35 ns
t
d21
Delay time, start to TXRDY active
t
SXA
14,15 C
L
= 75 pF 9
baudout
cycles
†
THRE = transmitter holding register empty; IIR = interrupt identification register.
modem control switching characteristics over recommended ranges of supply voltage and
operating free-air temperature, C
L
= 75 pF
PARAMETER ALT. SYMBOL FIGURE MIN MAX UNIT
t
d22
Delay time, WR MCR to output t
MDO
16 50 ns
t
d23
Delay time, modem interrupt to set INTRPT t
SIM
16 35 ns
t
d24
Delay time, RD MSR to reset INTRPT t
RIM
16 40 ns
t
d25
Delay time, CTS low to SOUT↓ 17 24
baudout
cycles
t
d26
Delay time, RCV threshold byte to RTS↑ 18 2
baudout
cycles
t
d27
Delay time, read of last byte in receive FIFO to RTS↓ 18 2
baudout
cycles
t
d28
Delay time, first data bit of 16th character to RTS↑ 19 2
baudout
cycles
t
d29
Delay time, RBRRD low to RTS↓ 19 2
baudout
cycles