Datasheet
TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053C – MAY 1989 – REVISED AUGUST 1999
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
interrupt identification register (IIR)
The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with
most microprocessors.
The ACE provides four prioritized levels of interrupts:
Priority 1 – Receiver line status (highest priority)
Priority 2 – Receiver data ready or receiver character time out
Priority 3 –Transmitter holding register empty
Priority 4–Modem status (lowest priority)
When an interrupt is generated, the IIR indicates that an interrupt is pending and indicates the type of interrupt
in its three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3 and
described in Table 4.
Bit 0: This bit can be used either in a hardwire prioritized or polled interrupt system. When this bit is cleared,
an interrupt is pending. When bit 0 is set, no interrupt is pending.
Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 4.
Bits 3 – 7: These bits in the interrupt identification register are not used and are always clear.
Table 4. Interrupt Control Functions
INTERRUPT
IDENTIFICATION
PRIORITY
INTERRUPT TYPE
INTERRUPT SOURCE
INTERRUPT RESET
REGISTER
LEVEL
INTERRUPT
TYPE
INTERRUPT
SOURCE
METHOD
BIT 2 BIT 1 BIT 0
0 0 1 None None None –
Overrun error, parity error,
Reading the line status
1 1 0 1 Receiver line status
,y,
framing error or break
Reading
the
line
stat
u
s
register
g
interrupt
register
1
0
0
2
Received data available
Receiver data available
Reading the receiver buffer
1
0
0
2
Recei
v
ed
data
a
v
ailable
Recei
v
er
data
a
v
ailable
g
register
Reading the interrupt
Transmitter holding register
Transmitter holding register
g
Identification register (if
0 1 0 3
Transmitter
holding
register
em
p
ty
Transmitter
holding
register
em
p
ty
g(
source of interrupt) or writing
empty
empty
)g
into the transmitter holding
g
register
Clear to send, data set
Reading the modem status
0 0 0 4 Modem status
ready, ring indicator, or data
Reading
the
modem
stat
u
s
register
carrier detect
register