Datasheet

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053C – MAY 1989 – REVISED AUGUST 1999
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
Table 1. Register Selection
DLAB
†
A2 A1 A0 REGISTER
0 L L L Receiver buffer (read), transmitter holding register (write)
0 L L H Interrupt enable register
X L H L Interrupt identification register (read only)
X L H H Line control register
X H L L Modem control register
X H L H Line status register
X H H L Modem status register
X H H H Scratch register
1 L L L Divisor latch (LSB)
1 L L H Divisor latch (MSB)
†
The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB
signal is controlled by writing to this bit location (see Table 3).
Table 2. ACE Reset Functions
REGISTER/SIGNAL
RESET
CONTROL
RESET STATE
Interrupt enable register RESET All bits cleared (0–3 forced and 4–7 permanent)
Interru
p
t identification register
RESET
Bit 0 is set
,
bits 1 and 2 are cleared
,
and bits 3–7
Interr
u
pt
identification
register
RESET
Bit
0
is
set,
bits
1
and
2
are
cleared,
and
bits
37
are permanently cleared
Line control register RESET All bits cleared
Modem control register RESET All bits cleared
Line status register RESET Bits 5 and 6 are set, all other bits are cleared
Modem status register RESET Bits 0–3 are cleared, bits 4–7 are input signals
SOUT RESET High
INTRPT (receiver error flag) Read LSR/RESET Low
INTRPT (received data available) Read RBR/RESET Low
INTRPT (transmitter holding register em
p
ty)
Read IIR/Write
Low
INTRPT
(transmitter
holding
register
empt
y
)
THR/RESET
Lo
w
INTRPT (modem status changes) Read MSR/RESET Low
OUT2 (interrupt enable) RESET High
RTS RESET High
DTR RESET High
OUT1 RESET High
Scratch register RESET No effect
Divisor latch (LSB and MSB) registers RESET No effect
Receiver buffer registers RESET No effect
Transmitter holding registers RESET No effect