Datasheet
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
interrupt identification register (IIR) (continued)
Table 4. Interrupt Control Functions
INTERRUPT
INTERRUPT
IDENTIFICATION
REGISTER
PRIORITY
INTERRUPT TYPE
INTERRUPT SOURCE
INTERRUPT RESET
IDENTIFICATION
REGISTER
PRIORITY
LEVEL
INTERRUPT TYPE
INTERRUPT SOURCE
INTERRUPT RESET
METHOD
BIT 2 BIT 1 BIT 0
LEVEL
METHOD
0 0 1 None None None −
Overrun error, parity error,
Reading the line status
1 1 0 1 Receiver line status
Overrun error, parity error,
framing error or break
Reading the line status
register
framing error or break
interrupt
register
1
0
0
2
Received data available
Receiver data available
Reading the receiver buffer
1
0
0
2
Received data available
Receiver data available
Buffer register
Reading the interrupt
Transmitter holding register
Transmitter holding register
Reading the interrupt
identification register (if
0 1 0 3
Transmitter holding register
empty
Transmitter holding register
empty
identification register (if
source of interrupt) or writing
into the transmitter holding
empty
empty
source of interrupt) or writing
into the transmitter holding
register
into the transmitter holding
register
Clear to send, data set
Reading the modem status
0 0 0 4 Modem status
Clear to send, data set
ready, ring indicator, or data
carrier detect
Reading the modem status
register
ready, ring indicator, or data
carrier detect
register
line control register (LCR)
The system programmer controls the format of the asynchronous data communication exchange through the
LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates
the need for separate storage of the line characteristics in system memory. The contents of this register are
summarized in Table 3 and are described in the following bulleted list.
D Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character.
These bits are encoded as shown in Table 5.
Table 5. Serial Character Word Length
Bit 1 Bit 0 Word Length
0 0 5 Bits
0 1 6 Bits
1 0 7 Bits
1 1 8 Bits
D Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When
bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated
is dependent on the word length selected with bits 0 and 1. The receiver checks the first stop bit only,
regardless of the number of stop bits selected. The number of stop bits generated, in relation to word length
and bit 2, is shown in Table 6.