Datasheet
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
accessible registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 3. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 3.
Table 3. Summary of Accessible Registers
REGISTER ADDRESS
Bit
O DLAB = 0 O DLAB = 0 1 DLAB = 0 2 3 4 5 6 7 O DLAB = 1
1
DLAB
= 0
Bit
No.
Receiver
Transmitter
Interrupt
Interrupt
Line
No.
Receiver
Buffer
Transmitter
Holding
Interrupt
Enable
Interrupt
Ident.
Line
Control
Modem
Line
Modem
Scratch
Divisor
Latch
Buffer
Register
Holding
Register
Enable
Register
Ident.
Register
Control
Register
Modem
Control
Line
Status
Modem
Status
Scratch
Register
Divisor
Latch
Latch
(MSB)
Register
(Read
Register
(Write
Register
IER
Register
(Read
Register
LCR
Control
Register
Status
Register
Status
Register
Register
Latch
(LSB)
(MSB)
(Read
Only)
(Write
Only)
IER
(Read
Only)
LCR
Register
Register
Register
(LSB)
RBR THR IER IIR LCR MCR LSR MSR SCR DLL DLM
Enable
Word
Enable
Received
“0” If
Word
Length
Data
Data
Delta
0
Data Bit 0*
Data Bit 0
Received
Data
“0” If
Interrupt
Length
Select
Data
Terminal
Data
Ready
Delta
Clear
Bit 0
Bit 0
Bit 8
0 Data Bit 0* Data Bit 0
Data
Available
Interrupt
Pending
Select
Bit 0
Terminal
Ready
Ready
(DR)
Clear
to Send
Bit 0 Bit 0 Bit 8
Available
Interrupt
(ERBF)
Pending
Bit 0
(WLSO)
Ready
(DTR)
(DR)
to Send
(DCTS)
Interrupt
(ERBF)
(WLSO)
(DTR)
(DCTS)
Enable
Enable
Transmitter
Word
Delta
Transmitter
Holding
Interrupt
Word
Length
Request
Overrun
Delta
Data
1
Data Bit 1
Data Bit 1
Holding
Register
Interrupt
ID
Length
Select
Request
to Send
Overrun
Error
Data
Set
Bit 1
Bit 1
Bit 9
1
Data Bit 1
Data Bit 1
Register
Empty
ID
Bit (0)
Select
Bit 1
to Send
(RTS)
Error
(OE)
Set
Ready
Bit 1
Bit 1
Bit 9
Empty
Interrupt
(ETBE)
Bit (0)
Bit 1
(WLS1)
(RTS)
(OE)
Ready
(DDSR)
Interrupt
(ETBE)
(WLS1)
(DDSR)
Enable
Trailing
Enable
Receiver
Interrupt
Number of
Parity
Trailing
EdgeRing
2
Data Bit 2
Data Bit 2
Receiver
Line Status
Interrupt
ID
Number of
Stop Bits
Out 1
Parity
Error
EdgeRing
Indicator
Bit 2
Bit 2
Bit 10
2
Data Bit 2
Data Bit 2
Line Status
Interrupt
ID
Bit (1)
Stop Bits
(STB)
Out 1
Error
(PE)
Indicator
(TERI)
Bit 2
Bit 2
Bit 10
Interrupt
(ELSI)
Bit (1)
(STB)
(PE)
(TERI)
Enable
Delta
Enable
Modem
Parity
Framing
Delta
Data
3
Data Bit 3
Data Bit 3
Modem
Status
0
Parity
Enable
Out 2
Framing
Error
Data
Carrier
Bit 3
Bit 3
Bit 11
3
Data Bit 3
Data Bit 3
Status
Interrupt
0
Enable
(PEN)
Out 2
Error
(FE)
Carrier
Detect
Bit 3
Bit 3
Bit 11
Interrupt
(EDSSI)
(PEN)
(FE)
Detect
(DDCD)
Even
Break
Clear
4
Data Bit 4
Data Bit 4
0
0
Even
Parity
Loop
Break
Interrupt
Clear
to Send
Bit 4
Bit 4
Bit 12
4 Data Bit 4 Data Bit 4 0 0
Parity
Select
Loop
Interrupt
(BI)
to Send
(CTS)
Bit 4 Bit 4 Bit 12
Select
(EPS)
(BI)
(CTS)
Transmitter
Data
5
Data Bit 5
Data Bit 5
0
0
Stick
0
Transmitter
Holding
Data
Set
Bit 5
Bit 5
Bit 13
5 Data Bit 5 Data Bit 5 0 0
Stick
Parity
0
Holding
Register
Set
Ready
Bit 5 Bit 5 Bit 13
Parity
Register
(THRE)
Ready
(DSR)
Set
Transmitter
Ring
6 Data Bit 6 Data Bit 6 0 0
Set
Break
0
Transmitter
Empty
Ring
Indicator
Bit 6 Bit 6 Bit 14
6
Data Bit 6
Data Bit 6
0
0
Break
0
Empty
(TEMT)
Indicator
(RI)
Bit 6
Bit 6
Bit 14
Divisor
Latch
Data
7
Data Bit 7
Data Bit 7
0
0
Divisor
Latch
Access
0
0
Data
Carrier
Bit 7
Bit 7
Bit 15
7
Data Bit 7
Data Bit 7
0
0
Access
Bit
0
0
Carrier
Detect
(DCD)
Bit 7
Bit 7
Bit 15
Bit
(DLAB)
(DCD)
*Bit 0 is the least significant bit. It is the first bit serially transmitted or received.