Datasheet

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  
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
Table 1. Register Selection
DLAB
†
A2 A1 A0 REGISTER
0 L L L Receiver buffer (read), transmitter holding register (write)
0 L L H Interrupt enable
X L H L Interrupt identification (read only)
X L H H Line control
X H L L Modem control
X H L H Line status
X H H L Modem status
X H H H Scratch
1 L L L Divisor latch (LSB)
1 L L H Divisor latch (MSB)
†
The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB signal is controlled
by writing to this bit location (see Table 3).
Table 2. ACE Reset Functions
REGISTER/SIGNAL
RESET
RESET STATE
REGISTER/SIGNAL
RESET
CONTROL
RESET STATE
Interrupt enable register Master reset All bits low (0−3 forced and 4−7 permanent)
Interrupt identification register
Master reset
Bit 0 is high, bits 1 and 2 are low, and bits 3 −7 are
Interrupt identification register Master reset
Bit 0 is high, bits 1 and 2 are low, and bits 3 −7 are
permanently low
Line control register All bits low
Modem control register Master reset All bits low
Line status register Master reset Bits 5 and 6 are high, all other bits are low
Modem status register Master reset Bits 0−3 are low, bits 4−7 are input signals
SOUT Master reset High
INTRPT (receiver error flag) Read LSR/MR Low
INTRPT (received data available) Read RBR/MR Low
INTRPT (transmitter holding register empty)
Read IIR/Write
Low
INTRPT (transmitter holding register empty)
Read IIR/Write
THR/MR
Low
INTRPT (modem status changes) Read MSR/MR Low
OUT2
Master reset High
RTS
Master reset High
DTR
Master reset High
OUT1
Master reset High
Scratch register Master reset No effect
Divisor latch (LSB and MSB) register Master reset No effect
Receiver buffer register Master reset No effect
Transmitter holding register Master reset No effect