Datasheet

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TL16C2550

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SLWS161E –JUNE 2005–REVISED NOVEMBER 2012

PIN FUNCTIONS (continued)

I/O DESCRIPTION

NAME PFB FN RHB

Data bus (bidirectional). These pins are the eight bit, 3-state

D0-D4 44 -48

2 - 6 27 - 31 data bus for transferring information to or from the controlling

I/O

7 - 9 32, 1, 2 CPU. D0 is the least significant bit and the first data bit in a

D5-D7 1 -3

transmit or receive serial data stream.

Data set ready (active low). These inputs are associated with

individual UART channels A and B. A logic low on these pins

DSRA, DSRB 39, 20 41, 25 – I indicates the modem or data set is powered on and is ready

for data exchange with the UART. The state of these inputs is

reflected in the modem status register (MSR).

Data terminal ready (active low). These outputs are

associated with individual UART channels A and B. A logic

low on these pins indicates that theTLl16C2550 is powered

DTRA, DTRB 34, 35 37, 38 – O on and ready. These pins can be controlled through the

modem control register. Writing a 1 to MCR bit 0 sets the

DTR output to low, enabling the modem. The output of these

pins is high after writing a 0 to MCR bit 0, or after a reset.

GND 17 22 13 Signal and power ground.

Interrupt A and B (active high). These pins provide individual

channel interrupts, INT A and B. INT A and B are enabled

when MCR bit 3 is set to a logic 1, interrupt sources are

enabled in the interrupt enable register (IER). Interrupt

INTA, INTB 30, 29 33. 32 21. 22 O

conditions include: receiver errors, available receiver buffer

data, available transmit buffer space or when a modem status

flag is detected. INTA-B are in the high-impedance state after

reset.

Read input (active low strobe). A high to low transition on IOR

will load the contents of an internal register defined by

IOR 19 24 14 I

address bits A0-A2 onto the TL16C2550 data bus (D0-D7) for

access by an external CPU.

Write input (active low strobe). A low to high transition on

IOW will transfer the contents of the data bus (D0-D7) from

IOW 15 20 12 I

the external CPU to an internal register that is defined by

address bits A0-A2 and CSA and CSB

12, 24, 25,

NC – 9 , 17 No internal connection

User defined outputs. This function is associated with

individual channels A and B. The state of these pins is

defined by the user through the software settings of the MCR

OPA, OPB 32, 9 35, 15 – O

logic 0 when the MCR-3 is set to a logic 1. INTA-B are set to

the 3-state mode and OP to a logic 1 when MCR-3 is set to a

logic 0. See bit 3, modem control register (MCR bit 3). The

output of these two pins is high after reset.

Reset. RESET will reset the internal registers and all the

outputs. The UART transmitter output and the receiver input

RESET 36 39 24 I will be disabled during reset time. See TL16C2550 external

reset conditions for initialization details. RESET is an active-

high input.

Ring indicator (active low). These inputs are associated with

individual UART channels A and B. A logic low on these pins

indicates the modem has received a ringing signal from the

RIA, RIB 41, 21 43 ,26 – I

telephone line. A low to high transition on these input pins

generates a modem status interrupt, if enabled. The state of

these inputs is reflected in the modem status register (MSR)

Product Folder Links :TL16C2550