Datasheet

Crystal
OSC
Buffer
Data Bus
Interface
A2 − A0
D7 − D0
CSA
CSB
IOR
IOW
INTA
INTB
TXRDYA
TXRDYB
RXRDYA
RXRDYB
RESET
XTAL1
XTAL2
BAUD
Rate
Gen
16 Byte Tx FIFO
16 Byte Rx FIFO
Tx
Rx
UART Channel A
BAUD
Rate
Gen
16 Byte Tx FIFO
16 Byte Rx FIFO
Tx
Rx
UART Channel B
CTSA
OPA, DTRA
DSRA, RIA, CDA
RTSA
CTSB
OPB, DTRB
DSRB, RIB, CDB
RTSB
V
CC
GND
TXA
RXA
TXB
RXB
UART Regs
UART Regs
TL16C2550
SLWS161E –JUNE 2005–REVISED NOVEMBER 2012 www.ti.com
TL16C2550 Block Diagram
DEVICE INFORMATION
PIN FUNCTIONS
PIN
I/O DESCRIPTION
NAME PFB FN RHB
A0 28 31 20 I Address 0 select bit. Internal registers address selection
A1 27 30 19 I Address 1 select bit. Internal registers address selection
A2 26 29 18 I Address 2 select bit. Internal registers address selection
Carrier detect (active low). These inputs are associated with
individual UART channels A and B. A low on these pins
CDA, CDB 40, 16 42, 21 – I indicates that a carrier has been detected by the modem for
that channel. The state of these inputs is reflected in the
modem status register (MSR).
Chip select A and B (active low). These pins enable data
transfers between the user CPU and the TL16C2550 for the
CSA, CSB 10, 11 16, 17 7, 8 I channel(s) addressed. Individual UART sections (A, B) are
addressed by providing a low on the respective CSA and
CSB pins.
Clear to send (active low). These inputs are associated with
individual UART channels A and B. A logic low on the CTS
pins indicates the modem or data set is ready to accept
transmit data from the 2550. Status can be tested by reading
CTSA, CTSB 38, 23 40, 28 25, 16 I
MSR bit 4. These pins only affect the transmit and receive
operations when auto CTS function is enabled through the
enhanced feature register (EFR) bit 7, for hardware flow
control operation.
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