Datasheet

TL16C2550
www.ti.com SLWS161E –JUNE 2005–REVISED NOVEMBER 2012
Figure 27. Typical Clock Circuits
Table 11. Typical Crystal Oscillator Network
Crystal R
P
RX2 (Optional) C1 C2
3.072 MHz 1 MΩ 1.5 kΩ 10–30 pF 40–60 pF
1.8432 MHz 1 MΩ 1.5 kΩ 10–30 pF 40–60 pF
16 MHz 1 MΩ 0 kΩ 33 pF 33 pF
Receiver Buffer Register (RBR)
The ACE receiver section consists of a receiver shift register (RSR) and a RBR. The RBR is actually a 16-byte
FIFO. Timing is derived from the input clock divided by the programmed devisor. Receiver section control is a
function of the ACE line control register.
The ACE RSR receives serial data from RX. The RSR then concatenates the data and moves it into the RBR
FIFO. In the TL16C450 mode, when a character is placed in the RBR and the received data available interrupt is
enabled (IER0 = 1), an interrupt is generated. This interrupt is cleared when the data is read out of the RBR. In
the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register.
Scratch Register
The scratch register is an 8-bit register that is intended for the programmer's use as a scratchpad in the sense
that it temporarily holds the programmer's data without affecting any other ACE operation.
Transmitter Holding Register (THR)
The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a 16-
byte FIFO. Timing is derived from the input clock divided by the programmed devisor. Transmitter section control
is a function of the ACE line control register.
The ACE THR receives data off the internal data bus and when the shift register is idle, moves it into the TSR.
The TSR serializes the data and outputs it at TX. In the TL16C450 mode, if the THR is empty and the transmitter
holding register empty (THRE) interrupt is enabled (IER1 = 1), an interrupt is generated. This interrupt is cleared
when a character is loaded into the register. In the FIFO mode, the interrupts are generated based on the control
setup in the FIFO control register.
Table 12. Typical Package Thermal Resistance Data
PACKAGE
48-Pin TQFP PFB θ
JA
= 50.1°C/W θ
JC
= 21.1°C/W
32-Pin TQFP RHB θ
JA
= xx°C/W θ
JC
= xx°C/W
44-Pin PLCC FN θ
JA
= 46.2°C/W θ
JC
= 22°C/W
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