Datasheet

TL16C2550

www.ti.com

SLWS161E –JUNE 2005–REVISED NOVEMBER 2012

Modem Status Register (MSR)

The MSR is an 8-bit register that provides information about the current state of the control lines from the

modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change

information; when a control input from the modem changes state, the appropriate bit is set. All four bits are

cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are

described in the following bulleted list.

• Bit 0: This bit is the change in clear-to-send (ΔCTS) indicator. ΔCTS indicates that the CTS input has

changed state since the last time it was read by the CPU. When ΔCTS is set (autoflow control is not enabled

and the modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control is

enabled (ΔCTS is cleared), no interrupt is generated.

• Bit 1: This bit is the change in data set ready (ΔDSR) indicator. ΔDSR indicates that the DSR input has

changed state since the last time it was read by the CPU. When ΔDSR is set and the modem status interrupt

is enabled, a modem status interrupt is generated.

• Bit 2: This bit is the trailing edge of the ring indicator (TERI) detector. TERI indicates that the RI input to the

chip has changed from a low to a high level. When TERI is set and the modem status interrupt is enabled, a

modem status interrupt is generated.

• Bit 3: This bit is the change in data carrier detect (ΔDCD) indicator. ΔDCD indicates that the DCD input to the

chip has changed state since the last time it was read by the CPU. When ΔDCD is set and the modem status

interrupt is enabled, a modem status interrupt is generated.

• Bit 4: This bit is the complement of the clear-to-send (CTS) input. When the ACE is in the diagnostic test

mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 1 (RTS).

• Bit 5: This bit is the complement of the data set ready (DSR) input. When the ACE is in the diagnostic test

mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 0 (DTR).

• Bit 6: This bit is the complement of the ring indicator (RI) input. When the ACE is in the diagnostic test mode

(LOOP [MCR4] = 1), this bit is equal to the MCR bit 2 (OUT1).

• Bit 7: This bit is the complement of the data carrier detect (DCD) input. When the ACE is in the diagnostic test

mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 3 (OUT2).

Programmable Baud Generator

The ACE contains a programmable baud generator that takes a clock input in the range between dc and 16 MHz

and divides it by a divisor in the range between 1 and (216 -1). The output frequency of the baud generator is

sixteen times (16 ×) the baud rate. The formula for the divisor is:

divisor = XIN frequency input P (desired baud rate × 16)

Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must

be loaded during initialization of the ACE in order to ensure desired operation of the baud generator. When either

of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.

Table 9 and Table 10 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072

MHz respectively. For baud rates of 38.4 kbits/s and below, the error obtained is small. The accuracy of the

selected baud rate is dependent on the selected crystal frequency (see Figure 27 for examples of typical clock

circuits).

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