Datasheet

TL16C2550

SLWS161E –JUNE 2005–REVISED NOVEMBER 2012

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at least one byte is written to the transmit FIFO.

• Bit 6: This bit is the transmitter empty (TEMT) indicator. TEMT bit is set when the THR and the TSR are both

empty. When either the THR or the TSR contains a data character, TEMT is cleared. In the FIFO mode,

TEMT is set when the transmitter FIFO and shift register are both empty.

• Bit 7: In the TL16C450 mode, this bit is always cleared. In the FIFO mode, LSR7 is set when there is at least

one parity, framing, or break error in the FIFO. It is cleared when the microprocessor reads the LSR and there

are no subsequent errors in the FIFO.

Modem Control Register (MCR)

The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is

emulating a modem. The contents of this register are summarized in Table 3 and are described in the following

bulleted list.

• Bit 0: This bit (DTR) controls the DTR output.

• Bit 1: This bit (RTS) controls the RTS output.

• Bit 2: This bit (OUT1) is reserved for output and can also be used for loopback mode.

• Bit 3: This bit (OUT2) controls the high-impedance state output buffer for the INT signal and the OP output.

When low, the INT signal is in a high-impedance state and OP is high. When high, the INT signal is enabled

and OP is low.

• Bit 4: This bit (LOOP) provides a local loop back feature for diagnostic testing of the ACE. When LOOP is set,

the following occurs:

– The transmitter TX is set high.

– The receiver RX is disconnected.

– The output of the TSR is looped back into the receiver shift register input.

– The four modem control inputs (CTS, DSR, CD, and RI) are disconnected.

– The four modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four

modem control inputs.

– The four modem control outputs are forced to the inactive (high) levels.

• Bit 5: This bit (AFE) is the autoflow control enable. When set, the autoflow control as described in the detailed

description is enabled. In the diagnostic mode, data that is transmitted is immediately received. This allows

the processor to verify the transmit and receive data paths to the ACE. The receiver and transmitter interrupts

are fully operational. The modem control interrupts are also operational, but the modem control interrupt's

sources are now the lower four bits of the MCR instead of the four modem control inputs. All interrupts are

still controlled by the IER.

The ACE flow can be configured by programming bits 1 and 5 of the MCR as shown in Table 8.

Table 8. ACE Flow Configuration

MCR BIT 5 (AFE) MCR BIT 1 (RTS) ACE FLOW CONFIGURATION

1 1 Auto-RTS and auto-CTS enabled (autoflow control enabled)

1 0 Auto-CTS only enabled

0 X Auto-RTS and auto-CTS disabled

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