Datasheet
TL16C2550
SLWS161E –JUNE 2005–REVISED NOVEMBER 2012
www.ti.com
Table 5. Interrupt Control Functions
INTERRUPT
IDENTIFICATION
PRIORITY INTERRUPT
REGISTER
INTERRUPT SOURCE INTERRUPT RESET METHOD
LEVEL TYPE
BIT BIT
BIT 1 BIT 0
3 2
0 0 0 1 None None None None
Receiver line Overrun error, parity error, framing
0 1 1 0 1 Read the line status register
status error, or break interrupt
Receiver data available in the
Received data
0 1 0 0 2 TL16C450 mode or trigger level Read the receiver buffer register
available
reached in the FIFO mode
No characters have been removed
from or input to the receiver FIFO
Character time-
1 1 0 0 2 during the last four character times, Read the receiver buffer register
out indication
and there is at least one character
in it during this time
Read the interrupt identification
Transmitter
register (if source of interrupt) or
0 0 1 0 3 holding register Transmitter holding register empty
writing into the transmitter holding
empty
register
Clear to send, data set ready, ring
0 0 0 0 4 Modem status Read the modem status register
indicator, or data carrier detect
Line Control Register (LCR)
The system programmer controls the format of the asynchronous data communication exchange through the
LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates
the need for separate storage of the line characteristics in system memory. The contents of this register are
summarized in Table 3 and described in the following bulleted list.
• Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character. These
bits are encoded as shown in Table 6.
Table 6. Serial Character Word Length
BIT 1 BIT 0 WORD LENGTH
0 0 5 bits
0 1 6 bits
1 0 7 bits
1 1 8 bits
• Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When bit
2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated is
dependent on the word length selected with bits 0 and 1. The receiver clocks only the first stop bit regardless
of the number of stop bits selected. The number of stop bits generated in relation to word length and bit 2 are
shown in Table 7.
Table 7. Number of Stop Bits Generated
BIT 2 Word Length Selectedby Bits 1 and 2 Number of Stop Bits Generated
0 Any word length 1
1 5 bits 1 1/2
1 6 bits 2
1 7 bits 2
1 8 bits 2
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