Datasheet

TL16C2550

SLWS161E –JUNE 2005–REVISED NOVEMBER 2012

www.ti.com

Table 4. Receiver FIFO Trigger Level

BIT 7 BIT 6 RECEIVER FIFO TRIGGER LEVEL (BYTES)

0 0 01

0 1 04

1 0 08

1 1 14

FIFO Interrupt Mode Operation

When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1, IER2 = 1), a receiver interrupt

occurs as follows:

1. The received data available interrupt is issued to the microprocessor when the FIFO has reached its

programmed trigger level. It is cleared when the FIFO drops below its programmed trigger level.

2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the

interrupt, it is cleared when the FIFO drops below the trigger level.

3. The receiver line status interrupt (IIR = 06) has higher priority than the received data available (IIR = 04)

interrupt.

4. The data ready bit (LSR0) is set when a character is transferred from the shift register to the receiver FIFO. It

is cleared when the FIFO is empty.

When the receiver FIFO and receiver interrupts are enabled:

1. FIFO time-out interrupt occurs if the following conditions exist:

(a) At least one character is in the FIFO.

(b) The most recent serial character was received more than four continuous character times ago (if two

stop bits are programmed, the second one is included in this time delay).

times before. This causes a maximum character received command to interrupt an issued delay of 160

ms at a 300-baud rate with a 12-bit character.

2. Character times are calculated by using the RCLK input for a clock signal (makes the delay proportional to

the baud rate).

3. When a time-out interrupt has occurred, it is cleared and the timer is cleared when the microprocessor reads

one character from the receiver FIFO.

4. When a time-out interrupt has not occurred, the time-out timer is cleared after a new character is received or

after the microprocessor reads the receiver FIFO.

When the transmitter FIFO and THRE interrupt are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur as

follows:

1. The transmitter holding register empty interrupt [IIR (3 -0) = 2] occurs when the transmit FIFO is empty. It is

cleared [IIR (3 -0) = 1] when the THR is written to (1 to 16 characters may be written to the transmit FIFO

while servicing this interrupt) or the IIR is read.

2. The transmitter holding register empty interrupt is delayed one character time minus the last stop bit time

when there have not been at least two bytes in the transmitter FIFO at the same time since the last time that

the FIFO was empty. The first transmitter interrupt after changing FCR0 is immediate if it is enabled.

Product Folder Links :TL16C2550