Datasheet

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TL16C2550

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SLWS161E –JUNE 2005–REVISED NOVEMBER 2012

Accessible Registers

The system programmer, using the CPU, has access to and control over any of the ACE registers that are

summarized in Table 2. These registers control ACE operations, receive data, and transmit data. Descriptions of

these registers follow Table 3.

Table 3. Summary of Accessible Registers

DLAB = 0 DLAB = 1

0 0 1 2 2 3 4 5 6 7 0 1

BIT

Transmitter Interrupt FIFO

Receiver

NO.

Holding Interrupt Ident Control Line Modem Line Divisor Divisor

Buffer Modem Status Scratch

(Write Register (Read (WriteOnl Register Register Register (LSB) (MSB)

(Read Only)

Only) Only) y)

RBR THR IER IIR FCR LCR MCR LSR MSR SCR DLL DLM

Enable Word

0 if Data

Received Data FIFO Length Data Terminal Delta Clear to

0 Data Bit 0

(1)

Data Bit 0 Interrupt Ready Bit 0 Bit 0 Bit 8

Available Enable Select Bit 0 Ready (DTR) Send (ΔCTS)

Pending (DR)

Interrupt (ERBI) (WLS0)

Enable

Transmitter Word

Receiver

Holding Interrupt Length Request to Overrun Delta Data Set

1 Data Bit 1 Data Bit 1 FIFO Bit 1 Bit 1 Bit 9

Reset

Interrupt (WLS1)

(ETBEI)

Enable

Transmitte Number of Trailing Edge

Receiver Line Interrupt Parity

2 Data Bit 2 Data Bit 2 r FIFO Stop Bits OUT1 Ring Indicator Bit 2 Bit 2 Bit 10

Status Interrupt ID Bit 2 Error (PE)

Reset (STB) (TERI)

(ELSI)

Enable Modem DMA Parity OUT2,

Interrupt Framing Delta Data Carrier

3 Data Bit 3 Data Bit 3 Status Interrupt Mode Enable OPcontrol, INT Bit 3 Bit 3 Bit 11

ID Bit 3

(2)

Error (FE) Detect (ΔDCD)

(EDSSI) Select (PEN) Enable

Even Parity Break

Clear to Send

4 Data Bit 4 Data Bit 4 0 0 Reserved Select Loop Interrupt Bit 4 Bit 4 Bit 12

(CTS)

(EPS) (BI)

Transmitte

Autoflow

r Holding Data Set Ready

5 Data Bit 5 Data Bit 5 0 0 Reserved Stick Parity Control Enable Bit 5 Bit 5 Bit 13

(AFE)

(THRE)

Receiver Transmitte

FIFOs Break Ring Indicator

6 Data Bit 6 Data Bit 6 0 Trigger 0 r Empty Bit 6 Bit 6 Bit 14

Enabled

(2)

Control (RI)

(LSB) (TEMT)

Divisor

Receiver Error in

FIFOs Latch Data Carrier

7 Data Bit 7 Data Bit 7 0 Trigger 0 RCVR Bit 7 Bit 7 Bit 15

Enabled

(2)

Access Bit Detect (DCD)

(MSB) FIFO(2)

(DLAB)

(1) Bit 0 is the least significant bit. It is the first bit serially transmitted or received.

(2) These bits are always 0 in the TL16C450 mode.

FIFO Control Register (FCR)

The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables

and clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signalling.

• Bit 0: This bit, when set, enables the transmitter and receiver FIFOs. Bit 0 must be set when other FCR bits

are written to or they are not programmed. Changing this bit clears the FIFOs.

• Bit 1: This bit, when set, clears all bytes in the receiver FIFO and clears its counter. The shift register is not

cleared. The 1 that is written to this bit position is self-clearing.

• Bit 2: This bit, when set, clears all bytes in the transmit FIFO and clears its counter. The shift register is not

cleared. The 1 that is written to this bit position is self-clearing.

• Bit 3: When FCR0 is set, setting FCR3 causes RXRDY and TXRDY to change from level 0 to level 1.

• Bits 4 and 5: These two bits are reserved for future use.

• Bits 6 and 7: These two bits set the trigger level for the receiver FIFO interrupt (see Table 4).

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