Datasheet
TL16C2550
SLWS161E –JUNE 2005–REVISED NOVEMBER 2012
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PRINCIPLES OF OPERATION
REGISTER SELECTION
Table 1. Register Selection
DLAB
(1)
A2 A1 A0 REGISTER
0 L L L Receiver buffer (read), transmitter holding register (write)
0 L L H Interrupt enable register
X L H L Interrupt identification register (read only)
X L H L FIFO control register (write)
X L H H Line control register
X H L L Modem control register
X H L H Line status register
X H H L Modem status register
X H H H Scratch register
1 L L L Divisor latch (LSB)
1 L L H Divisor latch (MSB)
(1) The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB signal is controlled by writing to this
bit location (see Table 2).
Table 2. ACE Reset Functions
REGISTER/SIGNAL RESET CONTROL RESET STATE
All bits cleared (0–3 forced and 4–7
Interrupt enable register Master reset
permanent)
Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared,
Interrupt identification register Master reset
and bits 4–5 are permanently cleared
FIFO control register Master reset All bits cleared
Line control register Master reset All bits cleared
Modem control register Master reset All bits cleared (6 -7 permanent)
Line status register Master reset Bits 5 and 6 are set; all other bits are cleared
Bits 0–3 are cleared; bits 4–7 are input
Modem status register Master reset
signals
TX Master reset High
INT Master reset, MCR3 Output buffer tristated
Interrupt condition (receiver error flag) Read LSR/MR Low
Interrupt condition (received data available) Read RBR/MR Low
Interrupt condition (transmitter holding
Read IIR/write THR/MR Low
register empty)
Interrupt condition (modem status changes) Read MSR/MR Low
OP Master reset High
RTS Master reset High
DTR Master reset High
Scratch register Master reset No effect
Divisor latch (LSB and MSB) registers Master reset No effect
Receiver buffer register Master reset No effect
Transmitter holding register Master reset No effect
RCVR FIFO MR/FCR1 – FCR0/DFCR0 All bits cleared
XMIT FIFO MR/FCR2 – FCR0/DFCR0 All bits cleared
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