Datasheet

t
d16
Parity Stop
Start
Data Bits
TXA, TXB
Start
t
d15
t
d17
t
d17
t
d18
t
d19
INT
(THRE)
IOW
(WR THR)
IOR
50% 50% 50% 50% 50%
50%
50%
50%
50%
50%
50%
t
d13
(see Note B)
t
d14
Sample Clock
(Internal)
RXA, RXB
(first byte that reaches
the trigger level)
Active
IOR
(RD RBR)
RXRDYA
, RXRDYB
See Note A
50%
50%50%
t
d13
(see Note B)
t
d14
Stop
Sample Clock
(Internal)
RXA, RXB
(first byte)
Active
IOR
(RD RBR)
RXRDYA
, RXRDYB
See Note A
50%
50%
50%
TL16C2550
www.ti.com SLWS161E –JUNE 2005–REVISED NOVEMBER 2012
TYPICAL CHARACTERISTICS (continued)
Figure 16. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
Figure 17. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 and FCR3 = 1 (Mode 1)
Figure 18. Transmitter Timing Waveforms
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