Datasheet

t
d13
(see Note A)
t
d14
Stop
Top Byte of FIFO
Sample Clock
(Internal)
RXA, RXB
Time-Out or
Trigger Level
Interrupt
Line Status
Interrupt (LSI)
t
d13
(FIFO at or above
trigger level)
(FIFO below
trigger level)
IOP
(RD LSR)
IOR
(RD RBR)
Active Active
t
d14
Previous Byte
Read From FIFO
50%
50%
50%50%
50%
50% 50%
t
d13
(see Note A)
t
d14
Stop
Data Bits 5−8
Sample Clock
(Internal)
RXA, RXB
Trigger Level
INT
(FCR6, 7 = 0, 0)
INT
Line Status
Interrupt (LSI)
t
d14
IOR
(RD LSR)
IOR
(RD RBR)
Active
Active
(FIFO at or above
trigger level)
(FIFO below
trigger level)
50%50%
50%
50%
50%
50%
TL16C2550
SLWS161E –JUNE 2005–REVISED NOVEMBER 2012 www.ti.com
TYPICAL CHARACTERISTICS (continued)
Figure 14. Receive First Byte (Sets DR Bit) Waveforms
Figure 15. Receive FIFO Bytes Other than the First Byte (DR Internal BIt already set) Waveforms
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