Datasheet
TL16C2550
SLWS161E –JUNE 2005–REVISED NOVEMBER 2012
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RECEIVER SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1) (2)
LIMITS
ALT. TEST
PARAMETER FIGURE 1.8 V 2.5 V 3.3 V 5 V UNIT
SYMBOL CONDITIONS
MIN MAX MIN MAX MIN MAX MIN MAX
t
d12
Delay time, RCLK to sample t
SCD
13 20 15 10 10 ns
Delay time, stop to set INT or read RBR to 13, 14, 15, RCLK
t
d13
t
SINT
1 1 1 1
LSI interrupt or stop to RXRDY↓ 16, 17 cycle
13, 14, 15,
t
d14
Delay time, read RBR/LSR to reset INT t
RINT
C
L
= 30 pF 100 90 80 70 ns
16, 17
baudout
t
d26
Delay time, RCV threshold byte to RTS↑ 23 C
L
= 30 pF 2
cycles
Delay time, read of last byte in receive FIFO baudout
t
d27
23 C
L
= 30 pF 2
to RTS↓ cycles
Delay time, first data bit of 16th character to baudout
t
d28
24 C
L
= 30 pF 2
RTS↑ cycles
baudout
t
d29
Delay time, RBRRD low to RTS↓ 24 C
L
= 30 pF 2
cycles
(1) In the FIFO mode, the read cycle (RC) = 1 baudclock (min) between reads of the receive FIFO and the status registers (interrupt
identification register or line status register)
(2) Not production tested.
TRANSMITTER SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1) (2)
LIMITS
ALT. TEST
PARAMETER FIGURE 1.8 V 2.5 V 3.3 V 5 V UNIT
SYMBOL CONDITIONS
MIN MAX MIN MAX MIN MAX MIN MAX
baudout
t
d15
Delay time, initial write to transmit start t
IRS
18 8 24 8 24 8 24 8 24
cycles
baudout
t
d16
Delay time, start to INT t
STI
18 8 10 8 10 8 10 10
cycles
t
d17
Delay time, IOW (WR THR) to reset INT t
HR
18 C
L
= 30 pF 70 60 50 8 50 ns
baudout
t
d18
Delay time, initial write to INT (THRE
(3)
) t
SI
18 16 34 16 34 16 34 16 34
cycles
Delay time, read IOR↑ to reset INT
t
d19
t
IR
18 C
L
= 30 pF 70 50 35 35 ns
(THRE
(3)
)
t
d20
Delay time, write to TXRDY inactive t
WXI
19, 20 C
L
= 30 pF 60 45 35 35 ns
baudout
t
d21
Delay time, start to TXRDY active t
SXA
19, 20 C
L
= 30 pF 9 9 9 9
cycles
t
SU4
Setup time, CTS↑ before midpoint of stop bit 22 30 20 10 10 ns
baudout
t
d25
Delay time, CTS low to TX↓ 22 C
L
= 30 pF 24 24 24 24
cycles
(1) In the FIFO mode, the read cycle (RC) = 1 baudclock (min) between reads of the receive FIFO and the status registers (interrupt
identification register or line status register)
(2) Not production tested.
(3) THRE = Transmitter Holding Register Empty; IIR = Interrupt Identification Register.
MODEM CONTROL SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
(1)
LIMITS
ALT. TEST
PARAMETER FIGURE 1.8 V 2.5 V 3.3 V 5 V UNIT
(2)
SYMBOL CONDITIONS
MIN MAX MIN MAX MIN MAX MIN MAX
t
d22
Delay time, WR MCR to output t
MDO
21 C
L
= 30 pF 90 70 60 50 ns
t
d23
Delay time, modem interrupt to set INT t
SIM
21 C
L
= 30 pF 60 50 40 35 ns
t
d24
Delay time, RD MSR to reset INT t
RIM
21 C
L
= 30 pF 80 60 50 40 ns
(1) Not production tested.
(2) A baudout cycle is equal to the period of the input clock divided by the programmed divider in DLL, DLM.
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