Datasheet
TL16C2550
www.ti.com
SLWS161E –JUNE 2005–REVISED NOVEMBER 2012
ELECTRICAL CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
5 V NOMINAL
High-level output
V
OH
I
OH
= –4 mA 4 V
voltage
(2)
V
OL
Low-level output voltage
(2)
I
OL
= 4 mA 0.4 V
I
I
Input current V
CC
= 5.5 V, V
SS
= 0, V
I
= 0 to 5.5 V, All other terminals floating 10 µA
High-impedance-state V
CC
= 5.5 V, V
SS
= 0, V
I
= 0 to 5.5 V, Chip slected in write mode
I
OZ
±20 µA
output current or chip deselcted
V
CC
= 5.5 V, T
A
= 0°C, RXA, RXB, DSRA, DSRB, CDA, CDB,
I
CC
Supply current CTSA, CTSB, RIA, and RIB at 2 V, All other inputs at 0.8 V, 7.5 mA
XTAL1 at 24 MHz, No load on outputs
C
i(CLK)
Clock input impedance
(3)
15 20 pF
C
O(CLK)
Clock output impedance
(3)
20 30 pF
V
CC
= 0, V
SS
= 0, f = 1 MHz, T
A
= 25°C, All other terminals
grounded
C
I
Input impedance
(3)
6 10 pF
C
O
Output impedance
(3)
10 20 pF
(1) All typical values are at V
CC
= 5 V and T
A
= 25°C.
(2) These parameters apply for all outputs except XTAL2.
(3) Not production tested.
TIMING REQUIREMENTS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
1.8 V 2.5 V 3.3 V 5 V
ALT. TEST
PARAMETER FIGURE UNIT
SYMBOL CONDITIONS
MIN MAX MIN MAX MIN MAX MIN MAX
t
w8
Pulse duration, RESET t
RESET
1 1 1 1 µs
t
w1
Pulse duration, clock high t
XH
10 40 25 20 18 ns
t
w2
Pulse duration, clock low t
XL
10 115 80 62 57 ns
t
cR
Cycle time, read (t
w7
+ t
d8
+ t
h7
) RC 12 115 80 62 57 ns
t
cW
Cycle time, write (t
w6
+ t
d5
+ t
h4
) WC 11 115 80 62 57 ns
t
w6
Pulse duration, IOW t
IOW
11 80 55 45 40 ns
t
w7
Pulse duration, IOR t
IOR
12 80 55 45 40 ns
t
SU3
Setup time, data valid before IOW↑ t
DS
11 25 20 15 15 ns
t
h3
Hold time, CS valid after IOW↑ t
WCS
11 0 0 0 0 ns
t
h4
Hold time, address valid after IOW↑ t
WA
11 20 15 10 10 ns
t
h5
Hold time, data valid after IOW↑ t
DH
11 15 10 5 5 ns
t
h6
Hold time, chip select valid after IOR↑ t
RCS
12 0 0 0 0 ns
t
h7
Hold time, address valid after IOR↑ t
RA
12 20 15 10 10 ns
t
d4
Delay time, CS valid before IOW↓ t
CSW
11 0 0 0 0 ns
t
d5
Delay time, address valid before IOW↓ t
AW
11 15 10 7 7 ns
t
d7
Delay time, CS valid to IOR↓ t
CSR
12 0 0 0 0 ns
t
d8
Delay time, address valid to IOR↓ t
AR
12 15 10 7 7 ns
t
d10
Delay time, IOR↓ to data valid t
RVD
12 C
L
= 30 pF 55 35 25 20 ns
t
d11
Delay time, IOR↓ to floating data t
HZ
12 C
L
= 30 pF 40 30 20 20 ns
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