Datasheet

THS8200
SLES032D –JUNE 2002–REVISED JUNE 2013 www.ti.com
7.6 Analog (DAC) Outputs
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
10 10
DAC resolution (11 bit (11 bit bits
internal) internal)
Best-fit Video (0.7 + 0.35 V bias) +.05/-1.2 +2/-2
INL Integral nonlinearity VDD_IO = 3.3 V, LSB
Generic (1.25 + 0 V bias) +1/-2.1 +5/-5
CLK = 500 kHz
Video (0.7 + 0.35 V bias) +0.2/−0.3 +1/−1
VDD_IO = 3.3 V,
DNL Differential nonlinearity LSB
CLK = 500 kHz
Generic (1.25 + 0 V bias) +0.3/-0.5 +1/−1
Power supply ripple
PSRR rejection ratio of DAC f = dc to 100 kHz
(1)
40 42 dB
output (full scale)
1 MHz sine wave,
49
offset bias off
1 MHz sine wave,
42
offset bias on
CLK = 205 MHz, -1 dB
10 MHz sine wave,
sine wave applied to active
49
offset bias off
Crosstalk between channels, offset bias
XTALK dB
channels
(2)
applied to all channels
10 MHz sine wave,
42
when turned on, 37.5 Ω
offset bias on
load on all channels
30 MHz sine wave,
48
offset bias off
30 MHz sine wave,
40.5
offset bias on
K
IMBAL
Imbalance between DACs CLK = 80 MHz
(3)
±2%
Video mode (bias offset
0.7 0.72
can be added)
DAC output compliance
V
OC
R
L
= 37.5 Ω
(4)
V
voltage (video only)
Generic mode (bias offset
1.25 1.3
cannot be added)
DAC output capacitance
C
O
5 pF
(pin capacitance)
DAC output current rise
t
ri
10 to 90% of full-scale, CLK = 80 MHz 3.5 4.2 ns
time
DAC output current fall
t
fi
10 to 90% of full-scale, CLK = 80 MHz 3.5 4.2 ns
time
Measured from falling edge of CLKIN to 50% of full-
t
d
Analog output delay 6.5 ns
scale transition
(5)
Measured from 50% of full scale transition on output to
t
sa
Analog output settling time 6.6 ns
output settling, within 2%
(6)
1 MHz, −1 dB FS digital sine input -55
Spurious-free dynamic
SFDR dB
range
10 MHz, −1 dB FS digital sine input -43
BW Bandwidth (3 dB) 90 MHz
E
glitch
Glitch energy Full-scale code transition at 205 MSPS 25 pVs
(1) PSRR is defined as 20 × log(ripple voltage at DAC output/ripple voltage at AVDD input). Limits from characterization only.
(2) Crosstalk spec applies to each possible pair of the 3 DAC outputs. Limit from characterization only.
(3) The imbalance between DACs applies to all possible pairs of the three DACs.
(4) Nominal values at R
FS
= R
FS(nom)
. Limit from characterization only. Excludes bias offset.
(5) This value excludes the digital process delay, t
D(D)
. Limit from characterization only. Data is clocked in on the rising edge of CLKIN.
Analog outputs become available on the falling edge of CLKIN.
(6) Limit from characterization only.
86 Electrical Characteristics Copyright © 2002–2013, Texas Instruments Incorporated
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