Datasheet

THS8200
www.ti.com SLES032D –JUNE 2002–REVISED JUNE 2013
7.5 Digital Inputs, DC Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
IH
High-level input current 1 µA
VDD_IO = 3.3 V,
I
IL
Low-level input current −1 µA
Digital inputs and CLK at 0 V for I
IL
,
I
IL(CLK)
Low-level input current, CLK 1 µA
Digital inputs and CLK at 3.6 V for I
IH
I
IH(CLK)
High-level input current, CLK −1 µA
C
I
Input capacitance T
A
= 25°C 5 pF
VDD_IO = 1.8 V 1.5
t
s
GY, RCr, BCb data inputs setup time nA
VDD_IO = 3.3 V 1.5
VDD_IO = 1.8 V 0.5
t
H
GY, RCr, BCb data inputs hold time nA
VDD_IO = 3.3 V 0.5
t
s
HS_IN, VS_IN, FID inputs setup time VDD_IO = 3.3 V
(1)
1.5 nA
t
H
HS_IN, VS_IN, FID inputs hold time VDD_IO = 3.3 V
(1)
0.5 nA
10-bit/20-bit 4:2:2 with CSM, CSC, 2x
73
(3)
interpolation active
t
d(D)
Digital process delay
(2)
30-bit 4:4:4 33
(3)
pixels
VESA clock mode (DLL, CSM, CSC, FIRs
9
bypassed)
(1) The HS_IN, VS_IN, and FID input setup/hold times are valid for 3.3-V I/O operation only. These sync inputs are not recommended for
use with 1.8-V I/O logic levels.
(2) Defined as the delay on Y pixel data, starting from the rising edge of CLKIN, until the clock period.
(3) CSC contribution: 8 pixels, CSM contribution: 1 pixel, 2x interpolation filter contribution: 18 pixels
Copyright © 2002–2013, Texas Instruments Incorporated Electrical Characteristics 85
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