Datasheet

THS8200
SLES032D –JUNE 2002–REVISED JUNE 2013 www.ti.com
7.3 Electrical Characteristics
over recommended operating conditions with f
CLK
= 205 MHz, R
FS
= Rfs(nom) (unless otherwise noted)
7.4 Power Supply
1-MHz FS ramp simultaneously applied to all three channels
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AV
DD
= 3.3 V, DV
DD
= 1.8 V, Video + no bias (700 mV) 94 98
VDD_DLL = 1.8 V,
Video + bias (1.05 V) 94 98
VDD_IO = 3.3 V,
Generic + no bias (1.25 V) 162 170
CLK = 80 MHz
Operating analog
IAV
DD
mA
AV
DD
= 3.3 V, DV
DD
= 1.8 V, Video + no bias (700 mV) 94 98
supply current
VDD_DLL = 1.8 V
Video + bias (1.05 V) 94 98
(DLL bypassed),
VDD_IO = 1.8 V,
Generic + no bias (1.25 V) 162 170
CLK = 200 MHz
AV
DD
= 3.3 V, DV
DD
= 1.8 V, Video + no bias (700 mV) 38 45
VDD_DLL = 1.8 V,
Video + bias (1.05 V) 38 45
VDD_IO = 3.3 V,
Generic + no bias (1.25 V) 38 45
CLK = 80 MHz
Operating digital
IDV
DD
mA
AV
DD
= 3.3 V, DV
DD
= 1.8 V, Video + no bias (700 mV) 89 95
supply current
VDD_DLL = 1.8 V
Video + bias (1.05 V) 89 95
(DLL bypassed),
VDD_IO = 1.8 V,
Generic + no bias (1.25 V) 89 95
CLK = 200 MHz
AV
DD
= 3.3 V, DV
DD
= 1.8 V, Video + no bias (700 mV) 1.7 2.2
VDD_DLL = 1.8 V,
Video + bias (1.05 V) 1.7 2.2
VDD_IO = 3.3 V,
Generic + no bias (1.25 V) 1.7 2.2
CLK = 80 MHz
Operating I/O
IVDD_IO mA
AV
DD
= 3.3 V, DV
DD
= 1.8 V, Video + no bias (700 mV) 1.7 2.2
supply current
VDD_DLL = 1.8 V
Video + bias (1.05 V) 1.7 2.2
(DLL bypassed),
VDD_IO = 1.8 V,
Generic + no bias (1.25 V) 1.7 2.2
CLK = 200 MHz
AV
DD
= 3.3 V, DV
DD
= 1.8 V, Video + no bias (700 mV) 4.9 5.6
VDD_DLL = 1.8 V,
Video + bias (1.05 V) 4.9 5.6
VDD_IO = 3.3 V,
Generic + no bias (1.25 V) 4.9 5.6
CLK = 80 MHz
Operating DLL
IVDD_DLL mA
AV
DD
= 3.3 V, DV
DD
= 1.8 V, Video + no bias (700 mV) 4.9 5.6
supply current
VDD_DLL = 1.8 V
Video + bias (1.05 V) 4.9 5.6
(DLL bypassed),
VDD_IO = 1.8 V,
Generic + no bias (1.25 V) 4.9 5.6
CLK = 200 MHz
AV
DD
= 3.3 V, DV
DD
= 1.8 V, Video + no bias (700 mV) 398 430
VDD_DLL = 1.8 V,
Video + bias (1.05 V) 398 430
VDD_IO = 3.3 V,
Generic + no bias (1.25 V) 641 660
CLK = 80 MHz
P
D
Power disspiation mW
AV
DD
= 3.3 V, DV
DD
= 1.8 V, Video + no bias (700 mV) 489 500
VDD_DLL = 1.8 V
Video + bias (1.05 V) 489 500
(DLL bypassed),
VDD_IO = 1.8 V,
Generic + no bias (1.25 V) 700 735
CLK = 200 MHz
84 Electrical Characteristics Copyright © 2002–2013, Texas Instruments Incorporated
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