Datasheet

MPEG Decoder/
Graphics Processor/
Video Memory
BPb[9:0]
GY[9:0]
RPr[9:0]
CLKIN
HS
VS
FID
THS8200
VS_OUT
HS_OUT
R/Pr
B/Pb
G/Y
Drive TV or
Computer Monitor
SDA
SCL
To an NTSC/PAL
Encoder
To an I
2
C
Master Device
D1CLK DO[9:0]
THS8200
www.ti.com SLES032D –JUNE 2002–REVISED JUNE 2013
6.2 DVI to Analog YPbPr/RGB Application
Together with a DVI receiver, this device forms a two-chip solution to convert video or graphics formats
sent over a DVI interface to an analog RGB or YPbPr format using embedded composite sync or separate
Hsync, Vsync. THS8200 connects gluelessly to a DVI receiver using its data input bus and HS_IN and
VS_IN terminals. TI DVI 1.0 (with HDCP) receivers provide a data enable (DE) signal that is high during
the active video window. The THS8200 can be configured to interpret this DE signal on its FID terminal to
automatically insert a user-programmable blanking-level amplitude outside the active video window on its
analog outputs; this blanking level can be correctly positioned for either RGB or YPbPr analog outputs.
The user can optionally perform color space conversion in the THS8200 and adjust offset and gain ranges
through the device's CSM block.
When sending (interlaced) video over DVI, the EIA-861 specification describes a method to derive the
fieldID signal—not directly available from a DVI1.0 (with HDCP) receiver—from the relative alignment of
the Hsync and Vsync signals. The THS8200 can be configured to derive internally the correct even/odd
field identification from Hsync/Vsync alignment according to this specification, instead of using the FieldID
signal on its FID input terminal. This avoids the need for additional glue logic in a DVI application.
6.3 Master vs Slave Timing Modes
In slave timing mode, the THS8200 output display timing is synchronized to the video data source. Display
timing output signals are based on input sync signals, either fed to the device on the dedicated Hsync,
Vsync, and FieldID (HS_IN, VS_IN, and FID) input terminals or based on SAV/EAV codes embedded in
the input video data.
Figure 6-3. Slave Operation Mode of THS8200
In master timing mode, the THS8200 generates two sets of output synchronization signals.
• HS_IN and VS_IN now become output signals to the video source (FID unused).
• HS_OUT and VS_OUT are still output signals to display device.
The intended purpose is that THS8200 requests video data from a source that requires external timing,
such as video memory.
Copyright © 2002–2013, Texas Instruments Incorporated Application Information 81
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