Datasheet

THS8200
www.ti.com SLES032D –JUNE 2002–REVISED JUNE 2013
dtg2_hlength(9:0): HS_OUT duration
{dtg2_hlength_msb_hdly_msb 0x71(7:6) and [00 0110 0000]
dtg2_hlength_lsb 0x70(7:0)}
Sets the duration of the HS_OUT output signal
dtg2_hdly(12:0): HS_OUT delay
{dtg2_hlength_msb_hdly_msb 0x71(4:0) and [0 0000 0000 0010]
dtg2_hdly_lsb 0x72(7:0)}
Sets the pixel value that the HS_OUT signal is asserted on.
Note: when programmed to a value higher than the total number of pixels per line, there will be no HS_OUT output.
dtg2_vlength1(9:0): VS_OUT duration, field 1
{dtg2_vlength1_msb_vdly1_msb 0x74(7:6) and [00 0000 0011]
dtg2_vlength1_lsb 0x73(7:0)}
Sets the duration of the VS_OUT output signal during progressive scan video modes or during the vertical blank interval of field 1 in
interlaced video modes.
dtg2_vdly1(10:0): VS_OUT delay, field 1
{dtg2_vlength1_msb_vdly1_msb 0x74(2:0) and [000 0000 0011]
dtg2_vdly1_lsb 0x75(7:0)}
Sets the line number that the VS_OUT signal is asserted on for progressive video modes or for field 1 of interlaced video modes.
Note: when programmed to a value higher than the total number of lines per frame, there is no VS_OUT output.
dtg2_vlength2(9:0): VS_OUT duration, field 2
{dtg2_vlength2_msb_vdly2_msb 0x77(7:6) and [00 0000 0000]
dtg2_vlength2_lsb 0x76(7:0)}
Sets the duration of the VS_OUT output signal during the vertical blank interval of field 2 in interlaced video modes. In progressive
video modes, this register must be set to all 0.
dtg2_vdly2(10:0): VS_OUT delay, field 2
{dtg2_vlength2_msb_vdly2_msb 0x77(2:0) and [111 1111 1111]
dtg2_vdly2_lsb 0x78(7:0)}
Sets the line number that the VS_OUT signal is asserted on for field 2 of interlaced scan video modes. For progressive scan video
modes, this register must be set to all 1.
dtg2_hs_in_dly(12:0): DTG horizontal delay
{dtg2_hs_in_dly_msb 0x79(4:0) and [0 0000 0011 1101]
dtg2_hs_in_dly_lsb 0x7A(7:0)}
Sets the number of pixels that the DTG startup is horizontally delayed with respect to HS input for dedicated timing modes or EAV
input for embedded timing modes.
Note: It is possible to delay startup past the end of a line when this delay is programmed higher than the total number of pixels per
line.
dtg2_vs_in_dly(10:0): DTG vertical delay
{dtg2_vs_in_dly_msb 0x7B(2:0) and [000 0000 0011]
dtg2_vs_in_dly_lsb 0x7C(7:0)}
Sets the number of lines that the DTG startup is vertically delayed with respect to VS input for dedicated timing modes or the line
counter value for embedded timing.
Note: It is possible to delay startup past the end of a frame when this delay is programmed higher than the total number of lines per
frame.
dtg2_pixel_cnt(15:0): Pixel count readback
{dtg2_pixel_cnt_msb 0x7D(7:0) and
dtg2_pixel_cnt_lsb 0x7E(7:0)}
Reports the number of clock 1x rising edges between consecutive Hsync input pulses
Copyright © 2002–2013, Texas Instruments Incorporated 75
I
2
C Registers
Submit Documentation Feedback
Product Folder Links: THS8200