Datasheet

THS8200
SLES032D –JUNE 2002–REVISED JUNE 2013 www.ti.com
5.2 Register Descriptions
Between { } are shown the name(s), subaddress(es) and bit position(s) where each register can be found
in the register map.
The default register value is shown between [ ] in binary format, and hexadecimal (h) and/or decimal (d)
notation where listed.
5.2.1 System Control (Sub-Addresses 0x02−0x03)
ver(7:0): Device version
{version 0x02(7..0)} [0000 0000]
The user can read this register to find out which version of THS8200 is in the system.
vesa_clk: Clock mode selection
{chip_ctl 0x03(7)} [0]
0 : Normal operation
1 : All clocks become identical, except for the half-rate clock, and the DLL is bypassed. This is used in VESA mode to support a direct
205-MHz input clock. No internal 2x interpolation is available. This mode should be used for all formats that require a >80 MSPS pixel
clock because the internal DLL for 2x clock generation is specified only up to 80 MSPS.
The half-rate clock is still internally generated if needed to allow, for example, 148-MHz 20-bit input (1080P).
dll_bypass: DLL bypass
{chip_ctl 0x03(6)} [0]
0 : DLL used for clock generation; normal operation with internally generated 2x clock. This mode should be selected for most video
formats when a 1x clock is available on the device clock input, and either 1x or 2x DAC operation is desired internally (as selected by
register data_ifir35_bypass)
1 : DLL bypassed for clock generation. In this case the clock input on the CLKIN pin is used directly as the 2x clock, rather than the
internally generated signal from the DLL.
vesa_colorbars: Color bar test pattern
{chip_ctl 0x03(5)} [0]
0 : normal operation
1 : Device generates color bar pattern; external video inputs are ignored. The color bar pattern is only supported in VESA PC graphics
mode, with the device configured in master mode
(chip_ms = 1).
dll_freq_sel: dll_freq_sel:
{chip_ctl 0x03(4)} [0]
Sets a frequency range for the DLL 2x clock generation. The DLL should not be used at >80 MHz. In this case the vesa_clk register
should be enabled. As a consequence, 2x video interpolation is not available for formats with >80 MHz pixel clock.
0 : high frequency range: pixel clock from 40−80 MHz
1 : low frequency range: pixel clock from 10−40 MHz
dac_pwdn: dac_pwdn:
{chip_ctl 0x03(3)} [0]
0 : normal operation
1 : DACs go into power-down state.
chip_pwdn: Chip power down
{chip_ctl 0x03(2)} [0]
0 : normal operation
1 : power down of all digital logic except I
2
C
64 Copyright © 2002–2013, Texas Instruments Incorporated
I
2
C Registers
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