Datasheet

THS8200
www.ti.com SLES032D –JUNE 2002–REVISED JUNE 2013
Table 5-1. I
2
C Register Map (continued)
REGISTER SUB-
R/W BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
NAME ADDRESS
dtg1_field_
R/W 0x3b dtg1_field_size(7:0)
size_lsb
dtg1_vesa_
R/W 0x3c dtg1_vesa_cbar_size(7:0)
cbar_size
DAC
dac_i2c_
dac_cntl_msb R/W 0x3d Reserved dac1_cntl(9:8) dac2_cntl(9:8) dac3_cntl(9:8)
cntl
dac1_cntl_lsb R/W 0x3e dac1_cntl(7:0)
dac2_cntl_lsb R/W 0x3f dac2_cntl(7:0)
dac3_cntl_lsb R/W 0x40 dac3_cntl(7:0)
CLIP/SHIFT/MULTIPLIER
csm_clip_
R/W 0x41 csm_clip_gy_low(7:0)
gy_low
csm_clip_
R/W 0x42 csm_clip_bcb_low(7:0)
bcb_low
csm_clip_
R/W 0x43 csm_clip_rcr_low(7:0)
rcr_low
csm_clip_
R/W 0x44 csm_clip_gy_high(7:0)
gy_high
csm_clip_
R/W 0x45 csm_clip_bcb_high(7:0)
bcb_high
csm_clip_
R/W 0x46 csm_clip_rcr_high(7:0)
rcr_high
csm_shift_gy R/W 0x47 csm_shift_gy(7:0)
csm_shift_bcb R/W 0x48 csm_shift_bcb(7:0)
csm_shift_rcr R/W 0x49 csm_shift_rcr(7:0)
csm_gy_ csm_gy_
csm_gy_ csm_mult csm_shift_ csm_of_
R/W 0x4a high_clip_ low_clip_ csm_mult_gy(10:8)
cntl_mult_ msb _ gy_on gy_on cntl
on on
csm_mult_
R/W 0x4b Reserved csm_mult_bcb(10:8) Reserved csm_mult_rcr(10:8)
bcb_rcr_ msb
csm_mult_
R/W 0x4c csm_mult_gy(7:0)
gy_lsb
csm_mult_
R/W 0x4d csm_mult_bcb(7:0)
bcb_lsb
csm_mult_
R/W 0x4e csm_mult_rcr(7:0)
rcr_lsb
csm_rcr_ csm_rcr_ csm_bcb_ csm_bcb _
csm_rcr_ csm_mult csm_mult_ csm_shift_ csm_shift_
R/W 0x4f high_clip_ low_clip_ high_clip_ low_clip_
bcb_cntl _ rcr_on bcb_on rcr_on bcb_on
on on on on
DISPLAY TIMING GENERATION, PART 2
dtg2_bp1_
R/W 0x50 Reserved dtg2_bp1(10:8) Reserved dtg2_bp2(10:8)
2_msb
dtg2_bp3_
R/W 0x51 Reserved dtg2_bp3(10:8) Reserved dtg2_bp4(10:8)
4_msb
dtg2_bp5_
R/W 0x52 Reserved dtg2_bp5(10:8) Reserved dtg2_bp6(10:8)
6_msb
dtg2_bp7_
R/W 0x53 Reserved dtg2_bp7(10:8) Reserved dtg2_bp8(10:8)
8_msb
dtg2_bp9_
R/W 0x54 Reserved dtg2_bp9(10:8) Reserved dtg2_bp10(10:8)
10_msb
dtg2_bp11_
R/W 0x55 Reserved dtg2_bp11(10:8) Reserved dtg2_bp12(10:8)
12_msb
Copyright © 2002–2013, Texas Instruments Incorporated 61
I
2
C Registers
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