Datasheet

THS8200
www.ti.com SLES032D –JUNE 2002–REVISED JUNE 2013
5 I
2
C Registers
5.1 I
2
C Register Map
R/W registers can be written and read.
R registers are read-only.
Table 5-1. I
2
C Register Map
REGISTER SUB-
R/W BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
NAME ADDRESS
0x00
Reserved
0x01
SYSTEM
version R 0x02 ver7 ver6 ver5 ver4 ver3 ver2 ver1 ver0
vesa_color dll_freq_ arst_
chip_ctl R/W 0x03 vesa_clk dll_bypass dac_pwdn chip_pwdn chip_ms
bars sel func_n
COLOR SPACE CONVERSION
csc_r11 R/W 0x04 csc_ric1(5:0) csc_rfc1(9:8)
csc_r12 R/W 0x05 csc_rfc1(7:0)
csc_r21 R/W 0x06 csc_ric2(5:0) csc_rfc2(9:8)
csc_r22 R/W 0x07 csc_rfc2(7:0)
csc_r31 R/W 0x08 csc_ric3(5:0) csc_rfc3(9:8)
csc_r32 R/W 0x09 csc_rfc3(7:0)
csc_g11 R/W 0x0a csc_gic1(5:0) csc_gfc1(9:8)
csc_g12 R/W 0x0b csc_gfc1(7:0)
csc_g21 R/W 0x0c csc_gic2(5:0) csc_gfc2(9:8)
csc_g22 R/W 0x0d csc_gfc2(7:0)
csc_g31 R/W 0x0e csc_gic3(5:0) csc_gfc3(9:8)
csc_g32 R/W 0x0f csc_gfc3(7:0)
csc_b11 R/W 0x10 csc_bic1(5:0) csc_bfc1(9:8)
csc_b12 R/W 0x11 csc_bfc1(7:0)
csc_b21 R/W 0x12 csc_bic2(5:0) csc_bfc2(9:8)
csc_b22 R/W 0x13 csc_bfc2(7:0)
csc_b31 R/W 0x14 csc_bic3(5:0) csc_bfc3(9:8)
csc_b32 R/W 0x15 csc_bfc3(7:0)
csc_offs1 R/W 0x16 csc_offset1(9:2)
csc_offs12 R/W 0x17 csc_offset1(1:0) csc_offset2(9:4)
csc_offs23 R/W 0x18 csc_offset2(3:0) csc_offset3(9:6)
csc_
csc_offs3 R/W 0x19 csc_offset3(5:0) c_uof_cnt l
bypass
TEST
st_
tst_cntl1 R/W 0x1a tst_offset Reserved
digbpass
tst_ tst_
tst_cntl2 R/W 0x1b tst_ydelay(1:0) Reserved Reserved Reserved Reserved
fastramp slowramp
DATA PATH
data_ data_ifir12 data_ifir35 data_
data_cntl R/W 0x1c data_fsadj data_dman_cntl(2:0)
clk6 56_on _bypass _bypass tristate656
DISPLAY TIMING GENERATION, PART 1
dtg1_y_
R/W 0x1d dtg1_y_blank(7:0)
sync1_lsb
Copyright © 2002–2013, Texas Instruments Incorporated 59
I
2
C Registers
Submit Documentation Feedback
Product Folder Links: THS8200