Datasheet
THS8200
SLES032D –JUNE 2002–REVISED JUNE 2013
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The I
2
C interface supports fast I
2
C, i.e., SCL up to 400 kHz.
WRITE FORMAT
S Slave address(w) A Sub-address A Data0 A ...... DataN-1 A P
S Start condition
Slave address(w) 0100 0000 (0x40) if I2CA = 0, or 0100 0010 (0x42) if I2CA = 1
A Acknowledge, generated by the THS8200
Sub-address Sub-address of the first register to write, length: 1 byte
Data0 First byte of the data
DataN-1 Nth byte of the data
P Stop condition
READ FORMAT
First write the sub-address, where the data must be read out to the THS8200 in the format as follows:
S Slave address(w) A Sub-address A P
S Slave address(r) A DataN AM Data(N+1) AM ...... NAM P
S Start condition
Slave address(r) 0100 0001 (0x41) if I2CA = 0, or 0100 0011 (0x43) if I2CA = 1
A Acknowledge, generated by the THS8200; if the transmission is successful, then A = 0, else A = 1
AM Acknowledge, generated by a master
NAM Not acknowledge, generated by a master
Sub-address Sub-address of the first register to read, length: 1 byte
Data0 First byte of the data read
DataN+1 Nth byte of the data read
P Stop condition
In both write and read operations, the sub-address is incremented automatically when multiple bytes are
written/read. Therefore, only the first sub-address needs to be supplied to the THS8200.
58 Detailed Functional Description Copyright © 2002–2013, Texas Instruments Incorporated
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