Datasheet

650 mV
350 mV
50 mV
0 mV
Active Video Period
Blank Level
Analog Output
Codes to DACs
960
512
700 mV
896
64
128
E’
cr
, E’
cb
Analog Output of Cr and Cb Channels With Sync Insertion
Blanking Interval
O
H
THS8200
SLES032D –JUNE 2002–REVISED JUNE 2013 www.ti.com
Figure 4-46. Analog Output of Cr and Cb Channels With Sync Insertion
The ac dynamic range during the active video period is the same on all channels, 700 mV. This means
that two different code ranges are mapped to the same analog output range. Because three DACs in the
THS8200 share a common full-scale adjust resistor, therefore, different input codes to the DAC result in
different analog outputs. To map two code ranges into a same analog output, the input code range must
be scaled in the CSM block.
4.8.6 Summary of Supported Video Formats
RGB WITHOUT RGB SYNC
RGB SYNC ON G YPbPr SYNC ON Y YPbPr SYNC ON ALL
SYNC ON ALL
Range of input 64 to 940 on Y; 64 to 940 on Y;
0 to 1023 64 to 940 64 to 940
codes 64 to 960 on Cr and Cb 64 to 960 on Cr and Cb
Peak level 700 mV or 1305 mV 1050 mV 1050 mV 1050 mV 1050 mV
Blank level 0 V 350 mV 350 mV 350 mV 350 mV
DC level shift
during active 0 350 mV 350 mV 350 mV 350 mV
video period
4.9 Test Functions
The user can activate a 75% SMPTE color bar test pattern when the device is configured in VESA mode
using the vesa_colorbars register setting. The width of each color bar can be programmed using the
dtg1_vesa_cbar_size register.
The digital logic in front of the DACs can be completely bypassed and the DACs can be driven directly
with levels programmed from the I
2
C interface by activating the dac_i2c_cntl register. In this case the
dac<n>_cntl registers set the DAC input codes. A fast or slow ramp signal can be internally generated and
sent to the DACs using tst_fastramp and tst_slowramp registers. This could be useful for a static DAC
linearity test.
Alternatively, the input bus can directly drive the DACs when the tst_digbypass register is activated for
tests at full speed.
The delay of the Y channel can be changed in YCbCr modes with respect to Cb and Cr channels by
programming the tst_ydelay register.
56 Detailed Functional Description Copyright © 2002–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: THS8200