Datasheet

THS8200
www.ti.com SLES032D –JUNE 2002–REVISED JUNE 2013
When the 525I preset is selected, the following line type sequence is active:
Breakpoints Line Type
4 NEQ_NEQ
7 BSP_BSP
10 NEQ_NEQ
20 FULL_NSP
263 ACTIVE_VIDEO
264 ACTIVE_NEQ
266 NEQ_NEQ
267 NEQ_BSP
269 BSP_BSP
270 BSP_NEQ
272 NEQ_NEQ
273 FULL_NEQ
282 FULL_NSP
283 NSP_ACTIVE
526 ACTIVE_VIDEO
frame_size = 1000001101; 525d
field_size = 00100000111; 263d
It can be seen this corresponds to the frame format shown, with 263 lines in digital field1 and 262 lines in
digital field2.
4.8 D/A Conversion
THS8200 contains three DACs with an internal resolution of 11 bits, and maximum speed of 205 MSPS.
This allows operation with all (H)DTV formats including 1080P, and PC graphics formats up to UXGA at
75 Hz.
The DAC output compliance can be selected between two full-scale ranges using the data_fsadj register.
DIGMUX selects DTG output data during nonvideo line types, except when dtg1_passthrough is active: in
this case video input data still is passed during the active video portion of certain line types, as identified in
Section 4.7.3 on the DTG line types.
THS8200 supports output in either RGB or YPbPr color spaces. When using RGB output, the
dtg2_rgb_mode_on register needs to be set. In this case an offset is added to all DAC output channels to
provide headroom for the negative sync. Nominally the blanking level is at 350 mV, and the 700 mV swing
extends upwards. Therefore peak white corresponds to 1.05 V. When YPbPr mode is selected on this
register, the offset is only added to the Y channel output; Pb and Pr outputs now have a video range from
0 to 700 mV with 0 V corresponding to internal DAC input code 0 (note that due to the CSM block this
could correspond to another device input code). The Cb and Cr chroma difference channels are thus
assumed to be offset binary encoded, not 2s complement.
Finally, the DTG mode determines whether the DIGMUX switches in output data from the DTG. For
example, in VESA mode the DACs are always driven by the video input bus. When the DTG overrides the
video input bus in SDTV or HDTV modes, the actual amplitude levels output by the DACs during this time
are user-programmable via the dtg1_<y,cbcr>_blank , dtg1_<y, cbcr>_sync_low, and dtg1_<y, cbcr>_high
registers.
Copyright © 2002–2013, Texas Instruments Incorporated Detailed Functional Description 51
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