Datasheet

THS8200
SLES032D –JUNE 2002–REVISED JUNE 2013 www.ti.com
7.7.3 Power for 1.25-V Output Compliance Without Bias at AVDD = 3.3 V, DVDD = 1.8 V, VDD_IO =
3.3 V, VDD_DLL = 3.3 V, 1-MHz Tone on All Channels .................................................. 89
7.7.4 Power for 1.25-V Output Compliance Without Bias at AVDD = 3.3 V, DVDD = 1.8 V, VDD_IO =
1.8 V, VDD_DLL = 3.3 V, 1-MHz Tone on All Channels .................................................. 90
7.8 Nonlinearity ................................................................................................................. 91
7.8.1 Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) for 700 mV Without Bias ............. 91
7.8.2 Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) for 700 mV + 350-mV Bias .......... 92
7.8.3 Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) for 1.25 V Without Bias ............... 93
7.9 Analog Output Bandwidth (sinx/x corrected) at f
S
= 205 MSPS ..................................................... 94
7.10 Output Compliance vs Full-Scale Adjustment Resistor Value ....................................................... 94
7.11 Vertical Sync of the HDTV 1080I Format Preset in First and Second Field, and Horizontal Line
Waveform Detail ........................................................................................................... 95
Revision History ......................................................................................................................... 96
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