Datasheet

>
HS (Input)
dtg2_hs_in_dly
RESET
Counter
RESET
Pixel
Counter
dtg2_hdly
>
=
=
RESET
Counter
dtg2_hlength
>
<
HS_Out
>
VS (Input)
dtg2_vs_in_dly
RESET
Counter
RESET
Line
Counter
>
=
=
RESET
Counter
dtg2_vlength
or
dtg2_vlength2
>
<
VS_Out
dtg2_vdly
or
dtg2_vdly2
THS8200
SLES032D –JUNE 2002–REVISED JUNE 2013 www.ti.com
Figure 4-15. THS8200 DTG VS/HS Output Generation
Note that both independent sets of delay registers allow accommodation of different input timing
references in slave mode. When the device is configured in master mode, the delay registers can
compensate for different external (frame memory) synchronization requirements.
4.7.2.3 Output Synchronization: Composite Sync
The composite sync is generated from a programmed sequence of (line type, breakpoint) combinations,
either user-programmed (in generic mode) or preset (in preset mode). The line type determines the
waveform shape at the output of the DAC(s) with programmable amplitudes and timings.
On each line, at the horizontal reference point of the DTG, the DTG decides where to start/stop the DTG-
generated data and where to pass input video data. For example, during an active video line, ancillary
data can be embedded in the digital stream outside the active video portion of the line, that it might be
necessary to convert to analog. Alternatively, during a nonactive video line, where normally the predefined
line type would be inserted, ancillary data might need to be passed during the active video portion of the
line.
The amplitudes of positive, negative sync excursions and of the negative serration, pre- and post-
equalization and broad pulses are independently programmable between G/Y and BPb, RPr channels.
Therefore sync insertion can be programmed on only the G/Y output or on all DAC outputs.
To limit the number of selection bits to select the line type, and because of the fact that a set of line types
can be defined that is mutually exclusive for SDTV and HDTV video modes, there are two DTG video
modes: SDTV and HDTV. There is a third DTG mode (VESA) which does not use the line type/breakpoint
state machine and only generates Hsync/Vsync outputs.
34 Detailed Functional Description Copyright © 2002–2013, Texas Instruments Incorporated
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