Datasheet

THS8200
www.ti.com SLES032D –JUNE 2002–REVISED JUNE 2013
4.7.3.13 FULL_NSP (Full Normal Sync Pulse) ........................................................... 46
4.7.3.14 NEQ_BSP (Negative Equalization Pulse/Broad Sync Pulse) ................................ 47
4.7.3.15 BSP_NEQ (Broad Sync Pulse/Negative Equalization Pulse) ................................ 47
4.7.3.16 FULL_NEQ (Full Negative Equalization Pulse) ................................................ 48
4.7.3.17 NSP_ACTIVE (Normal Sync Pulse/Active Video) ............................................. 48
4.7.3.18 ACTIVE_NEQ (Active Video/Negative Equalization Pulse) .................................. 49
4.7.3.19 ACTIVE VIDEO ..................................................................................... 49
4.8 D/A Conversion ............................................................................................................ 51
4.8.1 RGB Output Without Sync Signal Insertion/General-Purpose Application DAC ....................... 52
4.8.2 SMPTE-Compatible RGB Output With Sync Signal Inserted on G (Green) Channel ................. 53
4.8.3 SMPTE-Compatible Analog-Level Output With Sync Inserted on All RGB Channels ................. 54
4.8.4 SMPTE-Compatible YPbPr Output With Sync Signal Inserted on Y Channel Only ................... 55
4.8.5 SMPTE-Compatible YPbPr Output With Sync Signal Inserted on All Channels ....................... 55
4.8.6 Summary of Supported Video Formats ...................................................................... 56
4.9 Test Functions ............................................................................................................. 56
4.10 Power Down ................................................................................................................ 57
4.11 CGMS Insertion ............................................................................................................ 57
4.12 I
2
C Interface ................................................................................................................ 57
5 I
2
C Registers ..................................................................................................................... 59
5.1 I
2
C Register Map .......................................................................................................... 59
5.2 Register Descriptions ..................................................................................................... 64
5.2.1 System Control (Sub-Addresses 0x02−0x03) .............................................................. 64
5.2.2 Color Space Conversion Control (Sub-Addresses 0x04−0x19) .......................................... 65
5.2.3 Test Control (Sub-Addresses 0x1A−0x1B) .................................................................. 67
5.2.4 Data Path Control (Sub-Address 0x1C) ..................................................................... 68
5.2.5 Display Timing Generator Control, Part 1 (Sub-Addresses 0x1D−0x3C) ............................... 69
5.2.6 DAC Control (Sub-Addresses 0x3D−0x40) ................................................................. 71
5.2.7 Clip/Shift/Multiplier Control (Sub-Addresses 0x41−0x4F) ................................................. 72
5.2.8 Display Timing Generator Control, Part 2 (Sub-Addresses 0x50−0x82) ................................ 74
5.2.9 CGMS Control (Sub-Addresses 0x83−0x85) ............................................................... 77
5.3 THS8200 Preset Mode Line Type Definitions ......................................................................... 77
5.3.1 SMPTE_274P (1080P) ......................................................................................... 77
5.3.2 274M Interlaced (1080I) ....................................................................................... 77
5.3.3 296M Progressive (720P) ..................................................................................... 78
5.3.4 SDTV 525 Interlaced Mode ................................................................................... 78
5.3.5 SDTV 525 Progressive Mode ................................................................................. 78
5.3.6 SDTV 625 Interlaced Mode ................................................................................... 79
6 Application Information ...................................................................................................... 80
6.1 Video vs Computer Graphics Application .............................................................................. 80
6.2 DVI to Analog YPbPr/RGB Application ................................................................................. 81
6.3 Master vs Slave Timing Modes .......................................................................................... 81
7 Electrical Characteristics .................................................................................................... 83
7.1 Absolute Maximum Ratings .............................................................................................. 83
7.2 Recommended Operating Conditions .................................................................................. 83
7.3 Electrical Characteristics ................................................................................................. 84
7.4 Power Supply .............................................................................................................. 84
7.5 Digital Inputs, DC Characteristics ....................................................................................... 85
7.6 Analog (DAC) Outputs .................................................................................................... 86
7.7 Power Requirements ...................................................................................................... 87
7.7.1 Power for 700-mV DAC Output Compliance + 350-mV Bias at AVDD = 3.3 V, DVDD = 1.8 V,
VDD_IO = 3.3 V, VDD_DLL = 3.3 V, 1-MHz Tone on All Channels ..................................... 87
7.7.2 Power for 700-mV DAC Output Compliance + 350-mV Bias at AVDD = 3.3 V, DVDD = 1.8 V,
VDD_IO = 1.8 V, VDD_DLL = 3.3 V, 1-MHz Tone on All Channels ..................................... 88
Copyright © 2002–2013, Texas Instruments Incorporated Contents 3