Datasheet

THS8200
www.ti.com SLES032D –JUNE 2002–REVISED JUNE 2013
For the offset values, a value of 1/4 of the desired digital offset needs to be programmed in the individual
offset register, so a typical offset of 512 (offset over 1/2 of the video range) requires programming a value
of 128 decimal into the offset<1,2,3> registers, where again <1,2,3> defines the output channel affected,
with similar convention as shown previously.
Saturation logic can be switched in to avoid overflow and underflow on the result after color space
conversion using the csc_uof_cntl register.
An example of how to program the CSC follows. This also explains the numeric data formats.
CSC configuration example: HDTV RGB to HDTV YCbCr
The formulas for RGB to YCbCr conversion are:
• Yd = 0.2126*Rd + 0.7152*Gd + 0.0722*Bd
• Cb = −0.1172*Rd – 0.3942*Gd + 0.5114*Bd + 512
• Cr = 0.5114*Rd – 0.4646*Gd – 0.0468*Bd + 512
To program the red coefficient of channel 1 (Y) with the value of 0.2126 the following must be done:
1. Realize that this is a positive value so the sign bit of the integer part is 0 (bit 5 of csc_ric1 = 0).
2. Note that there is no integer portion of the coefficient (bit 4−bit 0 = 00000).
3. The binary representation of the fractional part can be constructed directly from the binary equivalent
of the fractional part multiplied by 1024 (0.2126 × 1024 = 217.7), rounded to the nearest integer (218)
and represented as a binary 10-bit number (00 1101 1010).
Using the above method all the registers for the CSC blocks can be programmed with the correct value for
RGB to YCbCr conversion. Below is a complete list of register values for the above conversion.
0.2126 → csc_ric1 = 00 0000 csc_rfc1 = 00 1101 1010
0.7152 → csc_gic1 = 00 0000 csc_gfc1 = 10 1101 1100
0.0722 → csc_bic1 = 00 0000 csc_bfc1 = 00 0100 1010
−0.1172 → csc_ric2 = 10 0000 csc_rfc2 = 00 0111 1000
−0.3942 → csc_gic2 = 10 0000 csc_gfc2 = 01 1001 0100
0.5114 → csc_bic2 = 00 0000 csc_bfc2 = 10 0000 1100
0.5114 → csc_ric3 = 00 0000 csc_rfc3 = 10 0000 1100
−0.4646 → csc_gic3 = 10 0000 csc_gfc3 = 01 1101 1100
−0.0468 → csc_bic3 = 10 0000 csc_bfc3 = 00 0011 0000
For the offsets necessary in the second and third equation, the csc_offset<n> registers need to be
programmed. Add 512 to the Cb and Cr channels. The value to be programmed is 1/4 of this offset in a
signed magnitude representation, thus 128 or csc_offset2 = csc_offset3 = 00 1000 0000.
Packing these individual registers into the I
2
C register map, the programmed values are:
SUBADDRESS REGISTER NAME VALUE
0x04 csc_r11 0000 0000
0x05 csc_r12 1101 1010
0x06 csc_r21 1000 0000
0x07 csc_r22 0111 1000
0x08 csc_r31 0000 0010
0x09 csc_r32 0000 1100
0x0A csc_g11 0000 0010
0x0B csc_g12 1101 1100
0x0C csc_g21 1000 0001
0x0D csc_g22 1001 0100
Copyright © 2002–2013, Texas Instruments Incorporated Detailed Functional Description 23
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