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THS8200

SLES032D –JUNE 2002–REVISED JUNE 2013

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4.3 Clock Generator (CGEN)/Clock Driver (CDRV)

The clock generator/clock driver blocks generate all on-chip clocks for 4:2:2 to 4:4:4 and 2x video

oversampling. The DMAN setting controls whether the input data is 4:2:2 or 4:4:4 sampled, and whether a

30-, 20- or 10-bit interface is used. This selection affects the clock input frequency assumed to be present

on CLKIN.

• 30-bit 4:4:4: 1x pixel clock. 4:2:2 to 4:4:4 interpolation should be bypassed. Optional 2x oversampling

is available for formats with pixel clock up to 80 MHz.

• 20-bit 4:2:2: 1x pixel clock. 4:2:2 to 4:4:4 interpolation should be switched in, and is available for

formats with pixel clock up to 150 MHz. Optional 2x oversampling available for formats with pixel clock

up to 80 MHz.

• 10-bit 4:2:2 (ITU): 1/2x pixel clock. 4:2:2 to 4:4:4 interpolation should be switched in, and is available

for formats with pixel clock up to 150 MHz. Optional 2x oversampling is available for formats with pixel

clock up to 80 MHz.

The internal DLL (delay-locked loop) generates the higher clock frequencies. The user should program the

input frequency range selection register, dll_freq_sel, according to the frequency present on CLK_IN when

using either or both interpolation/oversampling stages.

The 4:2:2 to 4:4:4 stage is switched in or bypassed, depending on the setting of data_ifir12_bypass

The THS8200 can perform color space conversion to RGB depending on the CSC setting. The

dtg2_rgbmode_on register should be set corresponding to the color space representation of the DAC

output.

The 2x oversampling stage is switched in or bypassed, depending on the setting of data_ifir35_bypass

The user should not enable the 2x oversampling stage when the CLK_IN frequency exceeds 80 MHz, as

is the case for the higher PC graphics formats and 1080P HDTV. In this case the DLL should be bypassed

using the vesa_clk register to disable the 2x frequency generation. As explained in the detailed register

map description for this register, it is still possible to support 20-bit 4:2:2 input in this mode (for example,

for 1080P).

A second bypass mode operation exists for the DLL, enabled by the dll_bypass register. When this

bypass mode is active, the CLKIN input is assumed to be 2x pixel frequency.

4.4 Color Space Conversion (CSC)

THS8200 contains a fully-programmable 3×3 multiply/add and 3×1 adder block that can be switched in for

all video formats up to a pixel clock frequency of 150 MHz. Color space conversion is thus available for all

DTV modes, including 1080P and VESA modes up to SXGA at 75 Hz (135 MSPS). The operation is done

after optional 4:2:2 to 4:4:4 conversion, and thus on the 1x pixel clock video data prior to optional 2x video

oversampling. The CSC block can be switched in or bypassed depending on the setting of register

csc_bypass.

Each of the nine floating point multiplier coefficients of the 3×3 multiply/add is represented as the

combination of a 6-bit signed binary integer part, and a 10-bit fractional part. The integer part is a signed

magnitude representation with the MSB as the sign bit. The fractional part is a magnitude representation;

see the following example.

The register nomenclature is: csc_<r,g,b> <i,f>c<1,2,3> where:

• <r,g,b> identifies which input channel is multiplied by this coefficient (r = red/Cr, g = green/Y,

b = blue/Cb input).

• <i,f> identifies the integer (i) or fractional (f) part of the coefficient.

• <1,2,3> identifies the output channel from the color space converter: 1 = Yd/Gd, 2 = Cb/Bd, 3 = Cr/Rd.

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