Datasheet

THS8200
SLES032D –JUNE 2002–REVISED JUNE 2013 www.ti.com
Table 2-1. Terminal Functions (continued)
TERMINAL
I/O
(1)
DESCRIPTION
NAME NO.
Serial clock line of I
2
C bus interface. Open-collector. Maximum specified clock speed is
SCL 64 B
400 kHz (fast I
2
C).
SDA 63 B Serial data line of I
2
C bus interface. Open-collector.
VDD_DLL 4 PWR Power supply of clock doubler, nominal 1.8 V
VDD_IO 19, 46, 70 PWR I/O ring power, 1.8 V or 3.3 V nominal
Vertical source synchronization. In slave timing mode, this is an input from the video data
VS_IN 44 I/O source. In master timing mode, this is an output to the video data source with programmable
timing and polarity, serving as a vertical data qualification signal to the video source.
Vertical sync output (to display). Irrespective of slave/master timing mode configuration, this is
VS_OUT 62 O
always an output with timing generated by the DTG.
12 Terminal Descriptions Copyright © 2002–2013, Texas Instruments Incorporated
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