Datasheet
R
Register
AR
R[9:0]
DAC
G
Register
B
Register
DAC
DAC
Configuration
Control
SYNC/BLANK
Control
Bandgap
Reference
G[9:0]
B[9:0]
CLK
M1
M2
AG
AB
COMP VREF
AV
DD
AV
SS
SYNC
BLANK
FSADJ
SYNC_T
Input
Formatter
DV
DD
DV
SS
THS8136
SLES236B –NOVEMBER 2008–REVISED APRIL 2013
www.ti.com
DETAILED DESCRIPTION
The THS8136 is a fast well-matched triple DAC with current outputs optimized for graphics and video
applications without sacrificing is usefulness as a generic DAC. The DAC output stages are designed to provide
direct drive of doubly-terminated 75-Ω loads (37.5 Ω). The full-scale output current of all three DACs is
determined by a single resistor connecting the FSADJ pin to AV
SS
(GND). A 3.8-kΩ resistor is suitable for most
applications requiring 700-mV output levels. Additional circuitry and digital input controls for analog sync and
blank level generation are provided for both RGB and YPbPr color spaces. A generic mode of operation is
provided for applications not requiring sync insertion. Figure 1 shows a block diagram of the device.
Figure 1. Functional Block Diagram
Generic DAC Mode Versus Sync Insertion Mode
When configured for sync insertion, the THS8136 provides additional dc bias on the DAC outputs to provide
headroom for negative bi-level sync insertion. Such bias might be undesirable in applications where no analog
sync insertion is required, since it results in additional power consumption and might prevent dc coupling of the
DAC outputs. In such cases, only triple DAC operation without dc bias (i.e., DAC input code 0 corresponding to
0-V output) might be preferred. Generic DAC mode is easily selected by connecting the SYNC and SYNC_T pins
to DV
DD
(or logic 1) and the M1 and M2 pins to DV
SS
(or logic 0). BLANK is functional in both generic mode and
sync insertion mode.
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