Datasheet

f Frequency MHz– –
300
310
320
330
340
350
360
370
380
390
400
0 50 100 150 200 250 300
P Power mW– –
CLK
RGB Data,
, , M2SYNC BLANK
t
s
t
h
T0 T1 T2 T3 T4 T5 T6 T7 T8
R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) R(8)
G(0) G(1) G(2) G(3) G(4) G(5) G(6) G(7) G(8)
B(0) B(1) B(2) B(3) B(4) B(5) B(6) B(7) B(8)
AR, AG, AB Output
Corresponding to R(0), G(0), B(0)
Data Path Latency = 7.5 CLK Cycles
R(0), G(0), B(0) Registered
CLK
THS8136
SLES236B –NOVEMBER 2008–REVISED APRIL 2013 www.ti.com
TYPICAL CHARACTERISTICS
Figure 7. Input Data Internally Latched on Rising Edge of CLK
(Data Path Latency is 7.5 CLK Cycles)
Figure 8. Input Data Registered on Rising Edge of CLK
Figure 9. Power vs Clock Frequency, RGB Sync Insertion, 1-MHz Input Tone on All Channels
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