Datasheet

THS8136
SLES236B –NOVEMBER 2008–REVISED APRIL 2013 www.ti.com
POWER SUPPLY ELECTRICAL CHARACTERISTICS
over recommended operating conditions, f
CLK
= 180 MHz, use of internal reference voltage V
REF
, R
FS
= R
FS(nom)
,
37.5-Ω load termination (unless otherwise noted)
PARAMETER TEST CONDITIONS
(1)
MIN TYP
(2)
MAX
(3)
UNIT
CLK = 80 MSPS 65 72
Generic (700 mV)
CLK = 180 MSPS 65 72
CLK = 80 MSPS 110 112
Operating supply current,
I
AVDD
Generic (1.2 mV) mA
analog
CLK = 180 MSPS 110 112
CLK = 80 MSPS 94 102
Sync Insertion (700 mV + Sync)
CLK = 180 MSPS 94 103
CLK = 80 MSPS 13 16
Generic (700 mV)
CLK = 180 MSPS 31 36
CLK = 80 MSPS 14 16
Operating supply current,
I
DVDD
Generic (1.2 mV) mA
digital
CLK = 180 MSPS 31 37
CLK = 80 MSPS 13 16
Sync Insertion (700 mV + Sync)
CLK = 180 MSPS 31 36
CLK = 80 MSPS 238 290
Generic (700 mV)
CLK = 180 MSPS 270 329
CLK = 80 MSPS 388 434
P
D
Power dissipation Generic (1.2 mV) mW
CLK = 180 MSPS 419 475
CLK = 80 MSPS 334 398
Sync Insertion (700 mV + Sync)
CLK = 180 MSPS 366 441
(1) A multiburst RGB input test pattern was used in all cases.
(2) TYP current and P
D
measured at AV
DD
= 3.3 V and DV
DD
= 1.8 V.
(3) MAX current and P
D
measured at AV
DD
= 3.6 V and DV
DD
= 1.95 V.
DIGITAL INPUTS – DC ELECTRICAL CHARACTERISTICS
over recommended operating conditions, f
CLK
= 180 MHz, use of internal reference voltage V
REF
, R
FS
= R
FS(nom)
,
37.5-Ω load termination (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
IH
High-level input current AV
DD
= 3.3 V, DV
DD
= 1.8 V, Digital inputs at 1.95 V 1 µA
I
IL
Low-level input current AV
DD
= 3.3 V, DV
DD
= 1.8 V, Digital inputs at 0 V –1 µA
I
IH(CLK)
High-level input current, CLK AV
DD
= 3.3 V, DV
DD
= 1.8 V, CLK at 1.95 V –1 1 µA
I
IL(CLK)
Low-level input current, CLK AV
DD
= 3.3 V, DV
DD
= 1.8 V, CLK at 0 V –1 1 µA
C
I
Input capacitance T
A
= 25°C 5 pF
Setup time, data and control
t
s
1.5 ns
inputs
(1)
Hold time, data and control
t
h
500 ps
inputs
(1)
Digital process delay time from first
CLK
t
d(D)
registered color component of 7.5
periods
pixel
(2)
(1) Specified by characterization only.
(2) This parameter is specified by design. The digital process delay is defined as the number of CLK cycles required for the first registered
color component of a pixel, starting from the time of registering it on the input bus, to propagate through all processing and appear at the
DAC output drivers. The remaining delay through the IC is the analog delay t
d(A)
of the analog output drivers.
10 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: THS8136