Datasheet

THS8135

www.ti.com

SLAS343B –MAY 2001–REVISED APRIL 2013

Selection of Color Space and Input Formatter Configuration (Available in Video DAC and

Generic DAC Modes)

Input data to the device can be supplied from a 3x10b GBR or YCbCr input port. If the device is configured to

take data from all three channels, the data is clocked in at each rising edge of CLK. All three DACs operate at

the full clock speed of CLK.

In the case of 4:2:2 sampled data (for YCbCr data), the device can be fed over either a 2x10 bit or 1x10 bit

multiplexed input port. An internal demultiplexer routes the input samples to the appropriate DAC: Y at the rate of

CLK, Cb and Cr each at rate of 1/2 CLK.

According to ITU-R.BT-656, the sample sequence is Cb-Y-Cr-Y over a 1x10-bit interface (Y-port). The sample

sequence starts at the first rising edge of CLK after BLANK has been taken high (inactive). Note that in this case

the frequency of CLK is 2x the Y conversion speed and 4x the conversion speed of both Cr and Cb.

In the case of a 2x10 bit input interface, both the Y-port and the Cr-port are sampled on every CLK rising edge.

The Cr-port carries the sample sequence Cb-Cr. The sample sequence starts at the first rising edge of CLK after

BLANK has been taken high (inactive). Note that in this case the frequency of CLK is equal to the conversion

speed of Y and 2x the conversion speed of both Cr and Cb.

Table 6 shows the possible configurations of the input formatter, as determined by the internal M1_INT and

M2_INT signals. The color space selection also determines the position of the blanking level and is explained in

the next section.

Table 6. THS8135 RGB/YCbCr Color Space and Input Formatter Configuration

M1_INT M2_INT CONFIGURATION DESRIPTION

GBR mode 4:4:4. Data clocked in on each rising edge of CLK from G, B, and R

L L GBR 3x10b-4:4:4

input channels.

YCbCr mode 4:4:4. Data clocked in on each rising edge of CLK from Y, Cb, and Cr

L H YCbCr 3x10b-4:4:4

input channels.

YCbCr mode 4:2:2 2x10 bit. Data clocked in on each rising edge of CLK from Y

H L YCbCr 2x10b-4:2:2 channel. A sample sequence of Cb-Cr should be applied to the Cr port. At the first

rising edge of CLK after BLANK is taken high, Cb should be present on this port.

YCbCr mode 4:2:2 1x10 bit (ITU-R.BT-656 compliant). Data clocked in on each

rising edge of CLK from Y channel. A sample sequence of Cb-Y-Cr-Y should be

H H YCbCr 1x10b-4:2:2

applied to the Y port. At the first rising edge of CLK after BLANK is taken high, Cb

should be present on this port.

Selection of Full-Scale or Reduced-Scale ITU.BT601 Modes (Available in Video DAC Mode Only)

In video DAC mode, BLNK_INT sets the blanking level generated on the DAC outputs as shown in Table 7. This

allows imposing a blanking level on the analog outputs corresponding to either full-scale code range or a

reduced-scale code range compliant to ITU-R.BT601. The blanking level is correctly positioned for either RGB or

YCbCr configurations, determined from the M1/M2 setting.

For generic DAC mode, BLNK_INT control is not available and the device always generates an output level

during BLANK low assuming full-scale input code range.

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