Datasheet

THS8135
SLAS343B –MAY 2001–REVISED APRIL 2013 www.ti.com
Table 3. Video vs Generic Mode Selection
SYNC BLANK SYNC_T OPERATION MODE AND DAC OUTPUT
1 1 1 Generic DAC mode. Blanking override inactive.
Generic DAC mode. Blanking override active. Blanking level position is according to the codes of
1 0 1
Table 7, however no dc bias is present on the Y, R, G, and B outputs
1 1 0 Video DAC mode. Blanking override inactive
Video DAC mode. Blanking override active. Blanking level position is according to the codes of
1 0 0
Table 7, with dc bias present on the Y, R, G, and B outputs as shown in Figure 1 and Figure 3.
0 X 0 Video DAC mode. Negative sync inserted.
0 X 1 Video DAC mode. Positive sync inserted.
Device Configuration Using M1 and M2 in Video DAC Mode
In the video DAC mode, the configuration signals M1 and M2 are both sampled on the second rising edge of the
CLK input signal after a L → H or H → L transition on SYNC. Depending on the polarity of this last transition on
SYNC, M1 and M2 are interpreted differently by the THS8135, as shown in Table 4.
NOTE
In the THS8133, only M2 is a sampled signal while M1 is continuously interpreted. By
doing so here, the additional input control signal BLNK_INT is generated. See the
backward compatibility with the THS8133 section.
Table 4. Interpretation of M1 in Video DAC Mode
THEN M1 IS
INTERPRETED ON
IF LAST EVENT ON THE SECOND CLK
DESCRIPTION
SYNC IS: RISING EDGE
FOLLOWING THIS
EVENT AS:
Sets operation with full or video (ITU-R.BT601) - input code range that is, the full-scale
H → L BLNK_INT range is reached from either the 0-1023 10-bit input code range or the input code range of
Table 8, see also Table 7 for blanking level positions.
L → H M1_INT Sets device operation mode. See Table 6 and Table 7.
Table 5. Interpretation of M2 in VIdeo DAC Mode
THEN M2 IS
INTERPRETED ON
IF LAST EVENT ON THE SECOND CLK
DESCRIPTION
SYNC IS: RISING EDGE
FOLLOWING THIS
EVENT AS:
Sets sync Insertion mode: SYNC low enables sync generation on one (INS3_INT = L) or all
H → L INS3_INT
three (INS3_INT = H) DAC outputs. SYNC_T determines the sync polarity.
L → H M2_INT Sets device operation mode. See Table 6 and Table 7.
Device Configuration Using M1 and M2 in Generic DAC Mode
To simplify device configuration in the generic DAC mode, the M1 and M2 configuration pins are continuously
interpreted as M1_INT and M2_INT respectively, that is, their interpretation is not dependent on the last event on
SYNC and is not only sampled on the second rising CLK edge after a transition on SYNC. BLNK_INT and
INS3_INT controls are not available in generic mode. As a result, in generic DAC mode, the device always
operates with full-scale input range and no sync insertion is available.
M1_INT and M2_INT can be tied high or low externally to determine the input formatter setting and color space
for blank level positions. Blanking override is still available in generic DAC mode using the BLANK input. Generic
DAC mode only disables the dc bias for R, G, B, and Y component outputs.
Table 3 shows all combinations of these control signals. Note that when SYNC is low, it takes precedence over
BLANK.
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