Datasheet

THS8135
SLAS343B –MAY 2001–REVISED APRIL 2013 www.ti.com
Table 2. Terminal Functions (continued)
TERMINAL
I/O DESCRIPTION
NAME NO.
DV
SS
11 I Digital ground
Full-scale adjust control. The full-scale current drive on each of the output channels is determined
by the value of a resistor R
FS
connected between this terminal and AV
SS
. Figure 5 shows the
FSADJ 38 I
relationship between full-scale output voltage compliance and R
FS
for the nominal DAC termination
of 37.5 Ω.
GY0-GY9 36-27 I Green or Y pixel data input. Signals with index 0 denote the least significant bits.
Operation mode control 1.
In video DAC mode, the second rising edge on CLK after a transition on SYNC latches M1. The
interpretation is dependent on the polarity of the last SYNC transition:
SYNC L → H: latched as M1_INT
SYNC H → L: latched as BLNK_INT
M1 47 I
Together with M2_INT, M1_INT configures the device as shown in Table 4 for video DAC mode.
BLNK_INT determines if the device operates with the full- or reduced-scale input code range.
Together with the color space configuration, this sets the amplitude of the blanking level on the
analog output(s) as shown in Table 7.
In generic DAC mode, M1 is continuously interpreted as M1_INT, BLNK_INT control is not available
and the device always assumes full-scale input code range for blank level positioning.
Operation mode control 2.
In video DAC mode, the second rising edge on CLK after a transition on SYNC latches M2. The
interpretation is dependent on the polarity of the last SYNC transition:
SYNC L → H: latched as M2_INT
SYNC H → L: latched as INS3_INT
M2 48 I
Together with M1_INT, M2_INT configures the device as shown in Table 5 for video DAC mode.
When INS3_INT is high, the device inserts sync on all DAC outputs; when low, sync is inserted only
on the AGY output.
In generic DAC mode, M2 is continuously interpreted as M2_INT, INS3_INT control is not
applicable, because sync insertion is not available in generic DAC mode.
RCr0-RCr9 13-22 I Red or Cr pixel data input. Signals with index 0 denote the least significant bits.
Sync control input, active low. A rising edge on CLK latches SYNC. When asserted, only the AGY
output (when INS3_INT = L, see terminal M2) for sync-on-G/Y, or ARPr, AGY, and ABPb outputs
(when INS3_INT = H, see terminal M2) for sync-on-all, are driven to the sync level, irrespective of
SYNC 24 I
the values on the data or BLANK inputs. Therefore, SYNC should remain low for the whole duration
of sync, which is in the case of a tri-level sync both the negative and positive portion. See Figure 10
for timing control. SYNC control is only available in video DAC mode.
Sync tri-level control, active high. A rising edge on CLK latches SYNC_T. When asserted (high), a
positive sync (higher than blanking level) is generated when SYNC is low. When disabled (low), a
negative sync (lower than blanking level) is generated when SYNC is low. When generating a tri-
level (negative-to-positive) sync, an L->H transition on this signal positions the start of the positive
SYNC_T 25 I
transition. Figure 10 for timing control.
SYNC_T is also used to put the device in generic DAC mode: SYNC = H AND SYNC_T = H →
generic DAC mode. Therefore, the user should always drive SYNC_T low outside the sync period
when video DAC mode operation is intended.
Voltage reference for DACs. An internal voltage reference of nominally 1.2 V is provided, which
V
REF
37 O
requires an external 0.1-µF ceramic capacitor between VREF and AV
SS
.
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