Datasheet

THS8135
www.ti.com SLAS343B –MAY 2001–REVISED APRIL 2013
Analog (DAC) Outputs
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DAC resolution 10 bits
Static, best-fit, sync-on-all, video mode, RGB full-scale -1.1/0.9 -2/1.5
INL Integral nonlinearity Static, best-fit, sync-on-all, video mode, RGB ITU.R-BT601 -1.2/0.8 -2/1.5 LSB
Static, best fit, generic mode, 1.3 V -1.61/0.94 -2/1.5
Static, sync-on-all, video mode, RGB full-scale ±0.4 ±1
DNL Differential nonlinearity Static, sync-on-all, video mode, RGB ITU.R-BT601 ±0.5 ±1 LSB
Static, generic mode, 1.3 V -0.32/0.24
Power supply ripple
PSRR rejection ratio of DAC f = DC
(1)
38.5 dB
output (full scale)
f = 1 MHz -63
Crosstalk between
XTALK dB
channels
(2)
f = 30 MHz -39
Voltage reference
V
refo
1.13 1.15 1.16 V
output
VREF output
R
R
276.5 284 294 Ω
resistance
Video mode, RGB full-scale -2% 1.8% 2%
Imbalance between
K
IMBAL
CLK = 80 MSPS
(3)
DACs
Video mode, RGB ITU-R.BT601 -3% 2.8% 3%
Video mode, RGB full-scale 0.7
DAC output compliance
V
OC
Video mode, RGB ITU-R.BT601 0.817 V
voltage (video only)
(4)
Generic mode 1.3
AGY 27 28 29.3
Video mode, full-scale
RGB, sync-on-all
ABPb and ARPr 27 28 29.3
AGY 27 28 29.3
Video mode, full-scale
YCbCr, sync-on-all
ABPb and ARPr 18 18.67 19.5
I
FS
CLK = 80 MSPS
(5)
mA
Video mode, ITU- AGY 30 31.18 32.0
R.BT601RGB, sync-on-
ABPb and ARPr 30 31.18 32.3
all
Video mode, ITU- AGY 30 31.18 32.1
R.BT601 YCbCr, sync-
ABPb and ARPr 20 21.39 22.5
on-all
DAC output current rise
t
RDAC
CLK = 80 MSPS, 10 to 90% of full-scale 3.2 3.5 4.2 ns
time
DAC output current fall
t
FDAC
CLK = 80 MSPS, 10 to 90% of full-scale 3.2 3.5 4.2 ns
time
Measured from CLK = V
IH(min)
to 50% of full-scale
t
d(A)
Analog output delay 4 ns
transition
(6)
Analog output settling Measured from 50% of full scale transition on output to
t
S
15 ns
time output settling, within 2%
(7)
Spurious-free dynamic
SFDR 1 MHz, -1 dBFS digital sine input 55 dB
range
1 dB 50
BW Bandwidth MHz
3 dB 100
E
glitch
Glitch energy Full-scale code transition at 240 MSPS 25 pVs
(1) PSRR is measured with a 0.1-µF capacitor between the COMP and AVDD pin; with a 0.1-µF capacitor connected between the VREF
pin and AVSS. The ripple amplitude is within the range 100 mVp-p to 500 mVp-p with the DAC output set to full scale and a double-
terminated 75 Ω (= 37.5 Ω) load. PSRR is defined as 20 x log(ripple voltage at DAC output/ripple voltage at AVDD input). Limits from
characterization only.
(2) Crosstalk spec applies to each possible pair of the three DAC outputs. Limits are from characterization only.
(3) The imbalance between DACs applies to all possible pairs of the three DACs.
(4) Values at R
FS
= R
FS(nom)
. Limits from characterization only.
(5) Values at R
FS
= R
FS(nom)
.
(6) This value excludes the digital process delay, t
D(D).
Limits from characterization only.
(7) Limit from characterization only. Measured on Y channel with other channels not driven.
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